similar to: [LLVMdev] Scilab to Verilog

Source: xen Version: 4.0.1~rc5-1 Severity: serious Justification: FTBFS User: debian-sparc at lists.debian.org Usertags: sparc Hi, your package no longer builds on sparc: | make[1]: Leaving directory `/build/buildd-sivp_0.5.2-2-sparc-3aHxSt/sivp-0.5.2' | SCI_DISABLE_TK=1 SCI_JAVA_ENABLE_HEADLESS=1 DOCBOOK_ROOT=/usr/share/sgml/docbook/stylesheet/xsl/nwalsh \ | /usr/bin/scilab -nw -f

Although the script doesn't generate identical results, it seems to get fairly close. The deviations for the Butterworth filter settings seem larger than for the equal loudness filter. This script requires OpenSource scilab which is available for Windows, Linux and MacOS. http://www.scilab.org/products/scilab/download Earl -------------- next part -------------- A non-text attachment was

Hello useRs, The results of the SORT function differ from Scilab/Matlab for Complex Numbers in my example. This design is the desirable in R? Thanks. Cleber r <- c( 1.7507+0.1689i, 1.7507-0.1689i, 1.3886+0.0000i, 1.0458+0.0792i, 1.0458-0.0792i, 0.8279+0.1861i, 0.8279-0.1861i, 0.8263+0.3731i, 0.8263-0.3731i, 0.6548+0.0000i ) > cbind(sort(r, d=T)) [,1] [1,]

https://bugs.freedesktop.org/show_bug.cgi?id=103217 Bug ID: 103217 Summary: Recent noveau causes errors with scilab 5.5.2 on NVIDIA G84GL [Quadro FX 570] Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component:

See http://wiki.scilab.org/Contributor_-_LLVM Ciao, Duncan.

If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is

Hi Nico, Yes, that's true! :-) I just listed it in order of short-comings of the existing compiler. I've been reading up on existing tools, and it would appear that a couple of commercial tools exist, most notably Xilinx AutoESL, which supports C, C++, SystemC and M-code. Others support better C functionality, e.g. c-to-verilog, which does not have the current

Hello, I previously sent this message, but it was in HTML only, so it was unreadable. I am thinking about making a compiler for a new HDL language, that will be more modern than VHDL and Verilog and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it in Ada. I don't know if it

Hi Jonas, >Thanks for your answers. > >In one year, I am going to have something like a semester project. >The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the

Hi, I'm not sure, but I think you should do point 'e' first - unless you want to implement 'a' to 'd' first for 1.5 and then again for 2.4. Best regards, Nico On Dec 29, 2008, at 1:44 PM, Elvis Dowson wrote: > Hi, > Would anyone happen to know if there are any efforts underway > at enhancing the Trident compiler? > > Some of the things that I

Hi, Would anyone happen to know if there are any efforts underway at enhancing the Trident compiler? Some of the things that I would like to add to the Trident compiler are : a. Support for compiling multiple C functions in an input file b. Support for parameter passing c. Support for functions returning results d. Support for a C++ front end, and C++ objects e. Updating the trident

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never

Hi Pavel, > If you are interested in HDLs perhaps you would be interested in Vlang? > I am currently working on Verilog fronted and I am looking for somebody with > VHDL interest to join the Vlang project. I have never heard about the Vlang project but it seems to be an interesting project. I think I could be interested to join this project and do the VHDL front-end. However, there are

Hello, I wanted to tell the LLVM developers list about http://www.c-to-verilog.com. I created this website to provide free on-line compilation of C into Verilog. I use LLVM as the C parser and optimizer. I have been working on this project for 2 years now. I would like to thank Chris, Vikram and the rest of the LLVM developers. I am very happy with the LLVM infrastructure, documentation, and

I'm currently looking to start my working on my major project for College. I want to create an audio CD archival/ playback server. There will be a base server and also several satellite players. I will be building a secondary server for my car. And in the car power is at a premium so I wanted true hardware support (unlike phatnoise which is software based). The car will support both

On Tue, 17 Jul 2007, Sarah Thompson wrote: > Do I understand correctly that there is nothing that the current gcc > front end generates that wouldn't fit an old-style GenericValue? I'm > wondering if this might be an interim approach that would avoid me > needing to rewrite huge amounts of code, and since we're not likely to > be supporting anything other than C and C++

Hi everybody, I was wondering if there would be interest in having a hardware IP implementing Opus (hardware as in VHDL/Verilog description)? Does that make sense? Several companies that seem to have an interest in Opus (such as Skype, Mozilla, Broadcom, Orange, Huawei) could thus have a dedicated, efficient, low-power solution for phones and tablets. As LTE is being deployed en masse, it

There is a 'feeling' on the opencores list that an audio decoder is desired. (MP3 gets mentioned occasionally, but has its patent problems etc...) http://www.opencores.org/ no audio projects are underway yet and I think a vorbis decoder will take a while but even if only a start is made then others may add to it. For their one year anniversary they will actually be doing a chip run and

Reid Spencer wrote: > Hi Sarah, > > On Tue, 2007-07-17 at 10:05 -0700, Sarah Thompson wrote: > >> Hi all, >> >> I've been quiet for a while, but I'm liable to be less so now that I'm >> starting on porting our model checker from LLVM 1.8 to 2.0. >> > > We missed you! :) > > Yes, apologies again for not making the