similar to: [LLVMdev] Questions on MachineFunctionPass and relaxation of pcrel calls (ARM/thumb2)

Hi, I have written a PassManager (IR) pass that seriously increases the size of the original IR code. As a result it seems that the generated machine code is incorrect (as of LLVM 3.5): The AsmPrinter generates the following instruction : adr r2, .LJTI4_0_0 when going through the MC streamer, I get a "fatal error: error in backend: out of range pc-relative fixup" . Apparently, the fixup

The linker is going off in the weeds trying to parse the dwarf unwind info. The CIE has: Leh_frame_common_begin0: .long 0 ## CIE Identifier Tag .byte 1 ## DW_CIE_VERSION .asciz "zLR" ## CIE Augmentation .byte 1 ## CIE Code Alignment Factor .byte 120 ## CIE Data Alignment

Hi James, > I've been trying to get a minimal test function to work, which simply > invokes _Unwind_RaiseException with a single clean-up landing pad. > However. when I run it my personality function is not getting called - > _Unwind_RaiseException simply returns apparently doing nothing. Looking > at the x86-64 assembly output from llc, I can see this is happening >

This is an interesting problem. The GC code is being converted into 'invokes' instead of calls: define i32 @main() gc "shadow-stack" { entry: %gc_frame = alloca %gc_stackentry.main %gc_currhead = load %gc_stackentry** @llvm_gc_root_chain %gc_frame.map = getelementptr %gc_stackentry.main* %gc_frame, i32 0, i32 0, i32 1 store %gc_map* getelementptr inbounds (%gc_map.0*

2010/1/22 Duncan Sands <baldrick at free.fr> > Hi James, > > > I've been trying to get a minimal test function to work, which simply >> invokes _Unwind_RaiseException with a single clean-up landing pad. However. >> when I run it my personality function is not getting called - >> _Unwind_RaiseException simply returns apparently doing nothing. Looking at

On Jan 21, 2014, at 3:20 PM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 21, 2014, at 2:20 PM, sebastien riou <matic at nimp.co.uk> wrote: > >> Hi, >> >> I would like to execute a MachineFunctionPass after all other passes >> which modify the machine code. >> In other words, if we call llc to generate assembly file, that pass >>

I am (desperately) trying to get used to using a Mac here at my new location. (Why *anyone* would ever use anything other than Linux, except under duress as I am, totally escapes me, but that's another story.) Fortunately much of the Mac OSX is actually Unix, so a civilized person can manage to carry on ... But there are some things. (Like this <expletive deleted> mailer ... But

Hi, I would like to execute a MachineFunctionPass after all other passes which modify the machine code. In other words, if we call llc to generate assembly file, that pass should run right before the "Assembly Printer" pass. Is there any official way to enforce this ? Best regards, Sebastien

Hello all, I need to modify llvm bytecode / native code just before it is emitted i.e. after all the regular operations and optimizations are done. I was told that this can be achieved by implementing a MachineFunctionPass. I searched the internet for some tutorials or some example MachineFunctionPass but found nothing. Kindly point some links, or anything that may help. Thank you. Regards,

Hi everyone, happy new year. This note is to announce that support for PC relative reloc tags for movw/movt is nearing completion (hopefully <48hrs!). This work is is from Jan Voung, David Meyer and myself. Unfortunately, to test this change, we need to patch ARM/AsmParser to address http://llvm.org/bugs/show_bug.cgi?id=8721 Locally, we have hacked up a solution to 8721, but its not ideal

On 10 January 2011 22:59, Jason Kim <jasonwkim at google.com> wrote: > Hi everyone, happy new year. > > This note is to announce that support for PC relative reloc tags for > movw/movt is nearing completion (hopefully <48hrs!). This work is is > from Jan Voung, David Meyer and myself. Hi Jason, Happy new year! That seems a long patch... with many changes... can't

-llvmcommits On Mon, Jan 10, 2011 at 3:21 PM, Renato Golin <renato.golin at arm.com> wrote: > Btw, I know this is for ELF printing, but can the same infrastructure > you're using to print the hi/lo be used to print relocation in Asm > output? Or is this a completely separate subject? Hi Renato, If I am understanding you correctly, then the answer is no, because .s output

On 10 January 2011 23:54, Jason Kim <jasonwkim at google.com> wrote: > If I am understanding you correctly, then the answer is no, because .s > output doesn't care about relocations per se... Hi Jason, That's not entirely true. ;) If you only use the GNU toolchain, that is correct. However, CodeSourcery's GCC changed a bit on how it works for ARM because the ARM toolchain

When addresses are a displacement from a constant (this can happen in device drivers), the resulting address gets folded rather than using base+displacement addressing. This results in code bloat. Example test attached. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: const-addr.ll URL:

I'm not authorized to file bugs. Would someone please enter this? Thank you, bagel Evan Cheng wrote: > Right. I am aware of this problem but am not sure about what to do about it. > It's common for a number 32-bit immediates in the same block with the same > lower or higher 16-bit. Since the immediates will not be split until late in > codegen, the target independent

To the right list this time. On Tue, Oct 18, 2016 at 12:43 PM Eric Christopher <echristo at gmail.com> wrote: > Hi Peter, > > Coming back to his now. > > > IFCC, the previous attempt to teach LLVM to emit jump tables, was removed > for complicating how functions are emitted, in particular requiring a > subtarget-specific instruction emitter available in

-----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of John Criswell Sent: Tuesday, September 11, 2012 1:42 PM To: Steve Checkoway Cc: LLVMdev at cs.uiuc.edu Subject: Re: [LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass ... > >> The code for adding the 32-bit instruction is: >> >>

On Sep 11, 2012, at 10:57 AM, John Criswell wrote: > I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code. Given that you don't actually

The actual size of even a MC instruction will change during relaxation--we don't choose between 8-bit jumps and wider jumps until relaxation. You can get the actual encoding of an MCInst via MCCodeEmitter, but if you expect relaxation to occur, or particularly if you're testing before register allocation, the size could only be an estimate and shouldn't be trusted for exact size.

On 9/11/12 12:10 PM, Stephen Checkoway wrote: > On Sep 11, 2012, at 10:57 AM, John Criswell wrote: > >> I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>"