similar to: [LLVMdev] Scheduler Integration Questions

On Apr 1, 2011, at 2:40 PM, Max Shawabkeh wrote: > Hello llvm-dev, > > I'm doing some experimentation on instruction scheduling and would like to use LLVM as a testbed, by integrating our existing (compiler-agnostic) scheduler into it. I have tinkered enough with the LLVM code to know how to create and run a new scheduler, access the DAG and target info, etc. However, I've come

Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>

Hi all, I'm currently investigating a bug which is causing an assert to fail in lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp. See https://llvm.org/bugs/show_bug.cgi?id=28753 for repro information. To my knowledge, this problem only occurs with the SystemZ target. I'm trying to determine whether the issue is the result of an edge case in the scheduling code itself, or if it's a

> I almost change all the instruction formats. It was a huge work. I am going > to compile and run it now. We have done the similar work[1] on this topic by gcc and we have start migrate our platform to LLVM. In my experience, you need to take care the follow part: * ARMBaseRegisterInfo::getRegPressureLimit * ARMBaseRegisterInfo::getRawAllocationOrder * CalleeSavedRegs *

Could you post the .ll file with the testcase? -Krzysztof On 7/29/2016 2:38 PM, Elliot Colp via llvm-dev wrote: > Hi all, > > I'm currently investigating a bug which is causing an assert to fail in > lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp. See > https://llvm.org/bugs/show_bug.cgi?id=28753 for repro information. > > To my knowledge, this problem only occurs with

I'm reposting this patch at the request of Evan. It fixes a problem with std::priority_queue and _GLIBCXX_DEBUG. -Dave -------------- next part -------------- A non-text attachment was scrubbed... Name: schedule_dag.diff Type: text/x-diff Size: 7731 bytes Desc: not available URL:

Sure, I've attached it to the bug report. Direct link is here: https://llvm.org/bugs/attachment.cgi?id=16840 - Elliot "llvm-dev" <llvm-dev-bounces at lists.llvm.org> wrote on 2016/07/29 03:46:41 PM: > From: Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> > To: llvm-dev at lists.llvm.org > Date: 2016/07/29 03:46 PM > Subject: Re: [llvm-dev]

Hi, We are working on a research project whose objective is developing a pre-allocation scheduling algorithm that achieves the optimal balance between exploiting ILP (hiding latencies) and minimizing register pressure.  A prototype of our algorithm has been implemented and integrated into an experimental version of LLVM 2.9. Our algorithm is based on a combinatorial optimization approach, which

Hello. I am new to the schedulers implemented in the back end of LLVM. I am trying to handle data hazards in my simple processor, with instructions that execute in 1 cycle. I have tried the standard post-RA scheduler, implemented in lib/CodeGen/PostRASchedulerList.cpp, (with a ScoreboardHazardRecognizer), but I have some issues with some consecutive instructions that are

Preallocation Instruction Scheduling with Register Pressure Minimization Using a Combinatorial Optimization Approach G. Shobaki, M. Shawabkeh and N. Abu-Rmaileh ACM Transactions on Architecture and Code Optimization (TACO). vol. 10, issue 3, Article 14 (Sept. 2013) http://dx.doi.org/10.1145/2512432 Regards Ghassan Shobaki, PH.D Assistant Professor Department of Computer Science Princess Sumaya

Hello, Still trying to write a custom scheduler, I stumbled accross a highly suspicious code in all schedulers. In both ScheduleDAGFast.cpp and ScheduleDAGRRList.cpp, one can find this piece of code: SUnit *CopyFromSU = CreateNewSUnit(NULL); and then in the same files: SUnit *CreateNewSUnit(SDNode *N) { [...] SUnit *NewNode = NewSUnit(N); And finally in ScheduleDAGSDNodes.cpp: SUnit

Hi, At the moment the same test is being ran twice - same output so pointless! I believe this may not be what was intended. The change below runs the virtual register test the second time on the Predecessor SUnit. Robert diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index f5fe168..6e888da ---

On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote: Now, to generate the best PPC schedules, there is one thing you may > want to override. The scheduler's priority function has a > HasReadyFilter attribute (enum). It can be overriden by specializing > hybrid_ls_rr_sort. Setting this to "true" enables proper ILP > scheduling, and maximizes the instructions that can

I almost change all the instruction formats. It was a huge work. I am going to compile and run it now. Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of Electrical and Computer Engineering University of Wisconsin-Madison E-mail: yazdanbakhsh

Thank you very much for the feedback, I tried to address the brought up issues in this updated proposal. In case you have any suggestions or comments feel free to tell me. Thanks in Advance Tilmann * Proposal for Google Summer of Code Project ** Using LLVM as a backend for QEMU's dynamic binary translation *** Terms: - host architecture: the architecture of the CPU QEMU is running on

Hello, here's my proposal for a GSoC project with LLVM. I'm happy for any feedback or advice you can give me. Thanks in Advance Tilmann * Proposal for Google Summer of Code Project ** Using LLVM as a backend for QEMU's dynamic binary translation *** Abstract: The goal of this project is to modify the QEMU dynamic binary translator to use components of the LLVM compiler

We are having a strange issue with LLVM 2.6 running on MSVC in debug mode. When compiling in debug mode, iterator debugging is turned on. In the case of std::priority_queue, iterator debugging checks to make sure that the queue is in proper order and will abort if it isn't. Recently, we have started to see this error in the DAG. Call Stack: SelectionDAGISel::runOnMachineFunction:339

Hi Tilmman, Thanks for submitting this. Here's some feedback. On Sun, 2007-03-25 at 00:41 +0100, Tilmann Scheller wrote: > Hello, > > here's my proposal for a GSoC project with LLVM. I'm happy for any > feedback or advice you can give me. > > Thanks in Advance > > Tilmann > > > * Proposal for Google Summer of Code Project > > ** Using

On May 25, 2010, at 2:58 PM, Smith, Tim wrote: > We are having a strange issue with LLVM 2.6 running on MSVC in debug mode. > > When compiling in debug mode, iterator debugging is turned on. In the case of std::priority_queue, iterator debugging checks to make sure that the queue is in proper order and will abort if it isn’t. > > Recently, we have started to see this error in

On Dec 19, 2011, at 6:51 AM, Hal Finkel <hfinkel at anl.gov> wrote: > On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote: > Now, to generate the best PPC schedules, there is one thing you may >> want to override. The scheduler's priority function has a >> HasReadyFilter attribute (enum). It can be overriden by specializing >> hybrid_ls_rr_sort. Setting this to