similar to: [LLVMdev] How to get register liveness information for each MachineBasicBlock

Hi all, I understand from the document that I should be able to configure llvm with only specific targets by passing -DLLVM_TARGETS_TO_BUILD=some-backend to cmake. However, I get the following errors whenever I don't include X86 in the target list: CMake Error at cmake/modules/LLVMConfig.cmake:127 (message): Library `X86' not found in list of llvm libraries. Call Stack (most recent

On Tue, Mar 15, 2011 at 6:34 PM, Dongrui She <sarevokcc at gmail.com> wrote: > However, I get the following errors whenever I don't include X86 in the > target list: on top of trunk, it seems cmake requires at least "native" (for yours, X86) target. (I reconfirmed with -DLLVM_TARGETS_TO_BUILD=ARM on x86) For workaround, you have to include "X86" always.

Hi all, I am trying to compute the liveness information for each MachineInstr in each MachineBasicBlock. I am not sure if it is correct. Here is how I compute the info. For each MachineBasicBlock MBB compute the LiveOuts of MBB by unioning all the LiveIns of its successors for each MachineInstr MI = MBB->rbegin() to MBB->rend() compute the LiveOuts of each MI by

Hi all, Sorry to bother those not interested in this problem. I have a problem while I want to reuse the liveness information after register allocation. When I use the livein_begin() from MachineBasicBlock to get the live-in registers after register alloction. I found that the liveness information is sometime incorrect. For example, some registers should be live-in to the machine basic block as

Hi all, I am working on an out-of-tree target. I am wondering if it is possible to force the register allocator (and/or spiller) to not break certain instruction sequence. For example: phys_reg = MI1 vreg1 vreg 2 = MI2 phys_reg Is there a way to tell RA/spiller not to insert COPY or spill between MI1 and MI2? I am using greedy register allocator and inline spiller. -- Regards, Dongrui

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the

Hi all, I'm developing a backend for a custom architecture. The target architecture has different memory for different data types(vector and scalar). So is it possible to maintain two different stacks, one for vector and the other for scalar? ---- Regards, Dongrui She -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, Have you try to directly describe such patterns in tblgen file? Like this: (brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset) MIPS backend does that. I also do this in my own backend, and seem to be working fine. On Mon, Jan 7, 2013 at 11:55 AM, Vikram Singh <vsp1729 at gmail.com> wrote: > I have seen that most of the targets do comparison and branching > in two separate

I want to be able to do two things with LLVM (both just before code emission): 1. Insert a MachineBasicBlock just before a MachineBasicBlock. There is a function called AddPredecessor(). However, the comment says that it does not update the actual CFG. I want to redirect all CFG edges that are incoming to this MachineBasicBlock to the new one I create, and add just one outgoing edge (no branch)

Where is the liveness analysis pass? I have been looking for days but cannot find anything. I just want to know transfer variables in and out of basic blocks, that are calculated using simple data flow equations. Thanks! -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180920/529bce15/attachment.html>

On Aug 13, 2012, at 8:34 AM, Sergei Larin <slarin at codeaurora.org> wrote: > Andy, > > Yes, this is what Arnold has suggested also, and from this point it looks > like it should work, but it will require parsing the bundle every time we > care to know whether this is a real use or a conditional def. This might > become awkward... but I guess I should provide a better

So what is the status about LiveVariables. Is there a plan to remove it? After searching in old lvm-dev-mails it is mentioned that LiveVariable still exists due to one pass needing it. And a comment in TargetPassConfig.cpp indicates that the pass in question is TwoAddressInstruction: // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed

I don't think you can. The BasicBlock is a member of MachineBasicBlock. It is not inherited, so it cannot be cast. The number of the MachineBasicBlock is not the same as any BasicBlock values. So MachineFunction::getMachineBasicBlock( BasicBlock::{get the number} ) cannot work. I do not see much in the basic block which can identify it. So you can search for it. typedef struct findBlock {

Also note: there may be multiple MachineBasicBlock's for a single BasicBlock. - David M On Fri, Oct 15, 2010 at 4:59 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > I don't think you can. > > The BasicBlock is a member of MachineBasicBlock. It is not inherited, > so it cannot be cast. The number of the MachineBasicBlock is not the > same as any BasicBlock values.

Hello all Currently I want to use the accurate liveness information when writing a *target independent* FunctionPass based on LLVM. The one I can find is LiveValues, a FunctionPass. But it doesn't use classic dataflow equation and can only provide approximate and conservative result. The another one is LiveVariables which use classic data flow equation, but it comes from Clang's analysis

The attached patch fixes bugs related to MachineBasicBlock::iterator. I don't have any test cases that reproduce on an X86 machine the problems that this patch fixes (these bugs were found when make check was run on a mips board). Please review. The first part just ensures that iterator I is not instr_end() before it invokes isInsideBundle(). The second part changes the signature of spillAll

Hi all, Two days ago MachineBasicBlock got ilistified. What does this mean and how does it affect you? Read on. MachineBasicBlock used to have a std::vector<MachineInstr*> to represent the instructions it constisted of. This representation has the following problems: 1) O(n) insertions/removals to/from anywhere but the end of a basic block (removals are very comomn in peephole

Hi all, While I using BuildMI with MachineBasicBlock as parameter, I made a mistake. The mistake was that the MachineBasicBlock of instruction, which is for insertion, is different with given MachineBasicBlock as parameter. I have thought if there is assertion code to check whether MachineBasicBlocks are same between instruction's MachineBasicBlock and given MachineBasicBlock as

Hello, we can get BasicBlock from MachineBasicBlock through MachineBasicBlock::getBasicBlock() function, but how can I get MachineBasicBlock of a BasicBlock? Thank you!

Hi all, I think that I came somewhat closer to a solution for splitting a MachineBasicBlock for a PSEUDO_CALL_R instruction and having a label to the new MBB: For following piece of code: --- typedef int callme_t(int a, int b); callme_t* c01; int foo(int a, int b) { return c01(a,b); // MachineBasicBlock will be split at call instruction } --- I have initially following correspondence: BB1