similar to: [LLVMdev] Creating tablegen patterns for intrinsics with no return value.

On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > I have intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted. Hi Micah, >From your description it sounds like machine dead code elimination is

> -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Monday, November 08, 2010 10:41 AM > To: Villmow, Micah > Cc: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Creating tablegen patterns for intrinsics with > no return value. > > > On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > > > I have intrinsic with no

I'm trying to write a store pattern that accepts both i32 and f32, however, when tablegen generates the code, it only generates the code for i32 only. def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; def MEM : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR, GPR); } def global_st :

You can tell LLVM that you have "sign extended" setCC results (all ones). Dan On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote: > On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: >> The IR produces correct results, but my backend does not and the >> only thing >> I can think of is that the IR is treating the

The main change from the patches I sent out earlier this week is support for guests that use the PIC. A callback for PIC irq ack handling is also introduced. Currently, there's no mechanism to register/unregister callers to the irq ack callbacks, but they can be added when there's more than one user for the functionality. Please review.

The main change from the patches I sent out earlier this week is support for guests that use the PIC. A callback for PIC irq ack handling is also introduced. Currently, there's no mechanism to register/unregister callers to the irq ack callbacks, but they can be added when there's more than one user for the functionality. Please review.

On Sep 23, 2008, at 10:44 AM, Villmow, Micah wrote: > I’m trying to write a store pattern that accepts both i32 and f32, > however, when tablegen generates the code, it only generates the > code for i32 only. > > def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; > def MEM : Operand<i32> { > let PrintMethod = "printMemOperand";

It seems to me that ipsecnat tunnel type is not complete. Latest drafts of ipsec nat-traversal use udp port 4500 for nat-traversal communications. (It''s called port floating). That is needed to get rid of ugly ipsec passthru devices. Now ipsecnat opens port udp/500 from any source port. And I think ipsecnat won''t work at all with gw zone defined? I''m not sure about

Hello, David > Ah, isLegalToFold saves us on trunk.  But we lose folding due to prefetching, > which is unfortunate. > > I am seeing the error with 2.5 (yes, we are upgrading!). > > I guess I'll have to backport some of the isLogalToFold logic. There was x86-only code at pre-2.6 times which was later moved into generic hook named "isLegalAndProfitableToFold". You

On Monday 22 February 2010 13:26:54 David Greene wrote: > On Monday 22 February 2010 13:06:39 Chris Lattner wrote: > > > Just wanted to clarify in case someone was wondering about this. > > > > I'm currently working in this area. What pattern is causing the cycle? > > Can I get a testcase? > > I'll see if I can generate one and file a PR. Ah,

Hi! I am trying to implement va_arg() on ppc32. Everything went smooth, except implementing va_arg() of 64bit int. Since i64 is not a legal type on ppc32 DAGTypeLegalizer::ExpandRes_VAARG() splits the va_arg(i64) into two i32 va_args. The problem with ppc32 va_arg is that it needs special "alignment" of its gpr pointer when the argument is i64. Ie. I need to know if I am lowering

We are syncing to 2.9 and we are hitting an with our backend in VerifySDNode in SelectionDAG.cpp. The first assert here is failing assert(!isa<MemSDNode>(N) && "Bad MemSDNode!"); Now, this is new to 2.9 and I am trying to understand what is invalid about what I am generating. What I generate has worked fine from LLVM version 2.4 until now without causing any issues.

Dear all I have written a function in C++ , equil_distC, that I am calling from an R script. In the last few days, R has repeatedly crashed when calling this function, or delivered obviously wrong outputs. However, when I restarted R after the crash, the results turned out to be OK most of the time although I had not modified the C++ code. Although the code runs correctly now, I am not sure

Right, later in the same file we have: // Reserve entries in the vector for each of the SUnits we are creating. This // ensure that reallocation of the vector won't happen, so SUnit*'s won't get // invalidated. // FIXME: Multiply by 2 because we may clone nodes during scheduling. // This is a temporary workaround. SUnits.reserve(NumNodes * 2); So for some reason *2 is

Oh yes you're right, I missed that :) But the point still hold. Amaury Pouly 2010/8/8 Eugene Toder <eltoder at gmail.com> > > Not only this code does not compile with NDEBUG set > > I may be missing something, but why does it not compile with -DNDEBUG? > assert() macro expands to noop when NDEBUG is set. > > Eugene > > On Sun, Aug 8, 2010 at 2:19 PM, Amaury

Hi Stefan, Thank you very much for answering my question! I followed your suggestion but the function still cannot return the correct result. I also set target-feature attributes for my function. I am using LLVM 6.0. It only prints out some random large numbers but the correct answer is supposed to be all 0. Can you please help me figure out what's going on here? Any help will be greatly

When I try to compile the olden bc's off the webpage I am getting undefined symbols. My compile script works as follows: #!/bin/sh echo "Generating assembly file." llc -f $1.bc echo "Assembling s file." /opt/SUNWspro/bin/cc -xarch=v9 -lm $1.s -o $1 echo "Removing s file." rm $1.s and here is an example of the symbol issues: Undefined first referenced symbol

Hi Joshua, Thanks for your great comment. I made up a ConstantVector in IR. Then I successfully use AVX intrinsics to retrieve the returned vector data. The remaining thing is that how to pass the vectors to LLVM function using intrinsics. Do you have any suggestions? Please forgive me if the question is too naive. I pasted below two IR I used. The first one works. The second one doesn't.

Hi Sanjoy, > Attached set of patches splits llvm.init.trampoline into an "init" > phase and an "adjust" phase, as discussed on the "Go on dragonegg" > thread. thanks for doing this. The patches look good, though the decomposition into individual patches is not that great (since things won't always work, in fact not even compile I think, with not all

Hi! Attached set of patches splits llvm.init.trampoline into an "init" phase and an "adjust" phase, as discussed on the "Go on dragonegg" thread. Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Split-intrinsics-and-DAG-nodes.patch Type: text/x-diff Size: 8808 bytes Desc: