similar to: [LLVMdev] [LLVMDev] [Question] The TargetRegisterClass has a confusing method.

Aye, I understand it's an index into an array, but what is the difference between the index i and the return value. Do I have to worry that register values from a TargetRegisterClass could be either zero based or some other base? Are there other methods that rely on zero based in the TargetRegisterClass? I thought register values were "global," but this transformation makes a

It's not too much of a problem then. I can make a DenseMap between the registers and my registers. It's just one more intermediate step for a lookup. I wish to mimic all the of the registers on the machine with my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register is used I can assign it easily. I know about alias register and those are taken care of ever so

On Sep 3, 2010, at 10:46 AM, Jeff Kunkel wrote: > It's not too much of a problem then. I can make a DenseMap between the registers and my registers. It's just one more intermediate step for a lookup. > > I wish to mimic all the of the registers on the machine with my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register is used I can assign it easily. I

How do I get the total number of machine registers? I have currently a MachineFunction and some derivatives. How are the machine registers ordered internally? Can I index them off of a zero based array or do I have to create a map to have them be zero based? Thanks, Jeff Kunkel -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote: > Ping. Anyone have any idea on how to fix this? Does your getAllocatableSet() return a BitVector that is at least getNumRegs() bits long? Otherwise this doesn't work: BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF); NonAllocatableRegs.flip();

llvm::TargetRegisterClass::getSize() llvm::TargetRegisterClass::getAllignment() will return the size and alignment of a virtual register used both in register allocation and stack slot assignment. llvm::TargetRegisterClass::alloc_order_begin() llvm::TargetRegisterClass::alloc_order_end() will give a list of the possible physical registers. When a virtual register is assigned a physical register

TargetRegisterInfo::getNumRegs(). Generally, it's best not to make any assumptions about the internal ordering or numbering if you can avoid it. What are you looking to do? -Jim On Sep 3, 2010, at 9:37 AM, Jeff Kunkel wrote: > How do I get the total number of machine registers? I have currently a MachineFunction and some derivatives. > > How are the machine registers ordered

So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific

Jakob, Here is my implementation of getAllocatableSet: BitVector AMDILRegisterInfo::getAllocatableSet(const MachineFunction& MF, const TargetRegisterClass *RC = NULL) const { BitVector Allocatable(getNumRegs()); Allocatable.clear(); return Allocatable; } Micah -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Monday, May 03, 2010 9:52 AM To:

Thanks for the information. I still don't know how do I partition registers into different classes from the virtual registers? For instance, I have the function who which iterates over the instructions, but I don't know how to write the function which returns the different register class. void RAOptimal::Gather(MachineFunction &Fn) { // Gather just iterates over the blocks,

On Sat, Aug 28, 2010 at 16:20:42 -0400, Jeff Kunkel wrote: > What I need to know is how to access the machine register classes. Also, I > need to know which virtual register is to be mapped into each specific > register class. I assume there is type information on the registers. I need > to know how to access it. MachineRegisterInfo::getRegClass will give you the TargetRegisterClass

Thank you for your help. I think I managed to create the instruction I wanted: // mov eax, 41 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), DAG.getConstant(41, MVT::i32), InFlag); InFlag = Chain.getValue(1); I don't understand though what InFlag is for. As I read the code, it even remains uninitialized when first passed to some node creation method.

On 1/28/11 8:14 AM, Qingan Li wrote: > Thanks for your help with me about the way to access type and size of > Value. > But, I want also know the interface for me to access the type or size > of virtual registers in the SSA form. > 1. I find no way to associate the virtual registers with the Value class. In the in-memory LLVM IR, all of the SSA values are C++ objects derived

Sorry to ask again, but I still can't get it right. The following code compiles and runs, but produces no instructions: Ops.push_back(DAG.getRegister(X86::EAX, MVT::i32)); Ops.push_back(DAG.getConstant(1, MVT::i32)); DAG.getNode(ISD::ADD, DAG.getVTList(MVT::i32), &Ops[0], Ops.size()); I reckon that has something to do with the fact that I am not using the Chain object. But as soon

Thanks for your help with me about the way to access type and size of Value. But, I want also know the interface for me to access the type or size of virtual registers in the SSA form. 1. I find no way to associate the virtual registers with the Value class. 2. I also tried to get the size of register nReg by: TargetRegisterClass::getSize(), where the TargetRegisterClass object is obtained by

Thanks to your help I've actually made some progress... Especially the SelectionDAGNodes.h was a good hint. But there are still some things that I can't figure out: // 'mov eax, 41' Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), DAG.getConstant(41, MVT::i32), InFlag); InFlag = Chain.getValue(1); // 'inc eax' SDValue eaxVal =

For spilling, I plan to use the Hack-Braun generalization of the furthest-first heuristic for SSA: http://pp.info.uni-karlsruhe.de/uploads/publikationen/braun09cc.pdf For coloring, there are a few different approaches you can take, e.g. dominator tree scan, puzzle-solving, or a modified graph coloring / coalescing heuristic like IRC. The best quality for the least amount of implementation effort

How do I get the TargetRegisterClass for a physical register? SSARegMap::getRegClass only works for virtual registers. -Dave

The allocator you are building, is it the Hack's and Goos's polynomial time algorithm? On Tue, Oct 5, 2010 at 7:14 PM, Cameron Zwarich <zwarich at apple.com> wrote: > There is nothing that currently handles this properly, as far as I know. If you have a phi > > c = phi(a, b) > > where a, b and c are all assigned distinct stack slots, then copies must be inserted in

On Jun 25, 2009, at 2:05 PM, Artjom K. wrote: > > Greetings, > > I am rather new to LLVM, so please excuse my limited knowledge about > it. > > Currently I am trying to modify the X86TargetLowering::LowerCALL > method by > inserting additional instructions before the call. > As far as I understand, nodes are created by calling the getNode > method on >