similar to: [LLVMdev] Patch - Allow calls that return i8 or i16. On SPU.

Hello, I have the following problem when trying to use rm: In a top level script file I have a loop iterating over some index. The loop is not contained within a function, so the scope of variables declared in the loop is global. Within this loop I generate several variables which should be removed at the end of each iteration. To do this, I wrote a function to clean up the workspace. An example

Hello, I'm seeing a miscompilation from the following code: declare <4 x float>* @getPtr() define <4 x float> @func() { %rv1 = call <4 x float>* @getPtr() %rv2 = call <4 x float>* @getPtr() %rv3 = load <4 x float>* %rv1 ret <4 x float> %rv3 } The load ends up loading from the pointer returned by the 2nd function call. I traced down the problem to

Dear R users I have run an regression and want to extract the p value of the F statistics, but I can find a way to do that. x<-summary(lm(log(RV2)~log(IV.m),data=b)) Call: lm(formula = log(RV2) ~ log(IV.m), data = b[[11]]) Residuals: Min 1Q Median 3Q Max -0.26511 -0.09718 -0.01326 0.11095 0.29777 Coefficients: Estimate Std. Error t value Pr(>|t|)

On 07/29/2013 06:28 AM, Matt Fleming wrote: > On Fri, 26 Jul, at 09:49:28AM, H. Peter Anvin wrote: >> Hmm... this might constrain the heap excessively if the SMT_TERMINAL >> cutoff is at the wrong place (because there will be just enough SMT_FREE >> to fit.) I'm wondering if we shouldn't use the highest of these two >> regions. > > Could you give an

Is there a way to force llvm to promote all smaller types to i32 instead of i16? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-609 One AMD Place Sunnyvale, CA. 94085 P: 408-749-3966 -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Tue, Feb 3, 2009 at 10:23 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Is there a way to force llvm to promote all smaller types to i32 instead of > i16? It should just work if i16 is also set to promote... what are you trying to do? -Eli

I want to promote i1 to i32 and not i16 as i32 is my native type and i16 is emulated, but I need to handle i16 as a special case so I don't want to promote it. I will see if what Bill pointed out is what I need. Micah -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman Sent: Tuesday, February 03, 2009 11:08 AM To:

"Villmow, Micah" <Micah.Villmow at amd.com> writes: > Sorry, <4 x i8> should convert to a <1 x i32>. Why? I'm really confused. Shouldn't this converts to a <4 x i32>? -Dave

The comments in the code state it should do bitcast, op, then bitcast, not extend, op and truncate. "SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { // Vector "promotion" is basically just bitcasting and doing the operation // in a different type. For example, x86 promotes ISD::AND on v2i32 to // v1i64." So following the same logic <4 x i8> bitcasts into a

Micah, I think that your patch is missing the necessary modifications in lib/VMCore/ValueTypes.cpp to EVT::getEVTString() and EVT::getTypeForEVT. -Hal On Fri, 27 Jul 2012 22:54:24 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > types. The problem is in the VectorLegalizer::PromoteVectorOp. The

I think that you attached the wrong patch. The attached patch is the one which adds the new MVT types. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for

Hi Xiantao, Some more nit-picking, though some of this is a bit more important to fixup. Cheers, Jes > +typedef struct thash_data { Urgh! argh! Please avoid typedefs unless you really need them, see Chapter 5 of Documentation/CodingStyle for details. > diff --git a/include/asm-ia64/kvm_host.h b/include/asm-ia64/kvm_host.h > new file mode 100644 > index 0000000..522bde0 > ---

Hi Xiantao, Some more nit-picking, though some of this is a bit more important to fixup. Cheers, Jes > +typedef struct thash_data { Urgh! argh! Please avoid typedefs unless you really need them, see Chapter 5 of Documentation/CodingStyle for details. > diff --git a/include/asm-ia64/kvm_host.h b/include/asm-ia64/kvm_host.h > new file mode 100644 > index 0000000..522bde0 > ---

Micah, One more thing ;) -- llvm::getEnumName in utils/TableGen/CodeGenTarget.cpp -Hal On Tue, 31 Jul 2012 21:02:02 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Ahh yep, thanks for catching that, new patch attached. > > > -----Original Message----- > > From: Hal Finkel [mailto:hfinkel at anl.gov] > > Sent: Tuesday, July 31, 2012 1:40 PM

>Though I am having trouble in understanding how  x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as >far as I can tell. The Type-Legalizer can handle vector types in the following ways: 1. Split - this splits vectors into two halves. For example on SSE4, <4 x i64> is split to <2 x i64> 2.

Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in

Ahh yep, thanks for catching that, new patch attached. > -----Original Message----- > From: Hal Finkel [mailto:hfinkel at anl.gov] > Sent: Tuesday, July 31, 2012 1:40 PM > To: Villmow, Micah > Cc: Developers Mailing List > Subject: Re: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> > > Micah, > > I think that your patch is missing the necessary

No, that is correct. I am adding the new types so that I can bitcast v2i8 into a v1i16 and then perform the 'and' operation and have legalize types turn the v1i16 into a scalar. Though I am having trouble in understanding how x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as far as I can tell. Micah

I don't know how your target architecture looks like, but I suspect that <4 x i8> should not be legalized to <1 x i32>. I think that what you are seeing is that <4 x i8> is first split into <2 x i8>, and later promoted to <2 x i32>. At the moment different targets can only affect type-legalization by declaring different legal types. A number of us discussed the

hi ambika, I am not sure about this solution as i just started working in this field. How about taking analogy of a problem which ask us to find nearest common parent of two nodes in a tree. Let me know if I can be corrected. - Anubhav intern IIT M B. Tech 4th year CSE VIT University, Vellore. On 31 May 2010 22:30, <llvmdev-request at cs.uiuc.edu> wrote: > Send LLVMdev mailing list