similar to: [LLVMdev] Adding multiples-of-8 integer types to MVT

Hi Ken, > Would there be any interest/opposition to extending the set of simple > integer types in MVT to include the missing multiples of 8 (up to 64 > bits)? That is: i24, i40, i48, i56? the type legalizer would need some work. Consider an architecture which has a 24 bit register. Then the type legalizer should legalize an i40 by first promoting it to an i48, then expanding that to

Grr... ---------- Forwarded message ---------- From: OvermindDL1 <overminddl1 at gmail.com> Date: Sat, Dec 5, 2009 at 5:58 PM Subject: Re: [LLVMdev] Adding multiples-of-8 integer types to MVT To: Duncan Sands <duncan.sands at math.u-psud.fr> On Sat, Dec 5, 2009 at 5:33 AM, Duncan Sands <duncan.sands at math.u-psud.fr> wrote: >>> Would there be any interest/opposition

>> Would there be any interest/opposition to extending the set of simple >> integer types in MVT to include the missing multiples of 8 (up to 64 >> bits)? That is: i24, i40, i48, i56? By the way, the integer type legalization logic should probably go like this: let T be an integer type. (1) If T is legal, do nothing. (2) If there is a legal integer type which is bigger (in

On Dec 2, 2009, at 12:32 PM, Ken Dyck wrote: > Would there be any interest/opposition to extending the set of simple > integer types in MVT to include the missing multiples of 8 (up to 64 > bits)? That is: i24, i40, i48, i56? > > Adding the types to MVT (and ValueTypes.td) would allow LLVM to be > targeted to architectures that have registers and operations of these > sizes

On Saturday, December 05, 2009 7:34 AM, Duncan Sands wrote, > > >> Would there be any interest/opposition to extending the > set of simple > >> integer types in MVT to include the missing multiples of 8 > (up to 64 > >> bits)? That is: i24, i40, i48, i56? > > By the way, the integer type legalization logic should > probably go like > this: let

On Wednesday, December 02, 2009 7:09 PM, Chris Lattner wrote: > > On Dec 2, 2009, at 12:32 PM, Ken Dyck wrote: > > > Would there be any interest/opposition to extending the set > of simple > > integer types in MVT to include the missing multiples of 8 > (up to 64 > > bits)? That is: i24, i40, i48, i56? > > > > Adding the types to MVT (and

hi every one, i have a very strange cpu that have 24-bits reigsters, but i cant see i24 in machine value type? and if defining it as MVT others will be ok? thank you very much

On Nov 13, 2009, at 6:45 AM, ether zhhb wrote: > hi every one, > > i have a very strange cpu that have 24-bits reigsters, but i cant see > i24 in machine value type? and if defining it as MVT others will be > ok? You'd want to add a new i24 MVT enum. -Chris

Hi all, hope someone can help me out with this. Background Introduction I have a data set consisting of data collected from a questionnaire that I wish to validate. I have chosen to use confirmatory factor analysis to analyse this data set. Instrument The instrument consists of 11 subscales. There is a total of 68 items in the 11 subscales. Each item is scored on an integer scale between 1 to 4.

Hi Ken, > What would do you think of modifying case (3) slightly as follows? well, that special cases the smallest legal type, which might not be a good idea. Imagine that i10 is legal, and also i32. Is it better to turn i40 into four lots of i10 or two lots of i32 with a promotion? Expansion is expensive, so two lots of i32 would be best. I suggest the following scheme: (3) Suppose T is

Instead of putting the burden on the back-ends to implement special lowering code, why not implement code in the legalizer that would automatically sign extend them to the next largest power of 2 integer if the specific integer types were not supported. This would then remove the need of the back-ends to implement anything as LLVM would just generate extend the values to i32/i64 silently. Micah

Do you mean MVT::getIntegerVT? Because I can not find getExtendedIntegerVT in the llvm source codes. I am excited seeing this function, however I have the following more questions. 1) You mention I will have to change not small amount of target indenpendent codegen codes to support this extended type. Are there any document to describe how to do such kind modification? I see there is a

Hi, > I am not sure how legalizer and friends deal with i24 / f24 as legal > types. the type legalizer currently assumes that all legal integer types have a power-of-two number of bits. I don't see any obstacles to making it more general though. First off, i24 would need to be added to the list of simple value types. Then the integer promotion and expansion logic would need to be

Hi all! Our target (a non-public DSP) has 40-bit integer registers, and our C front-end support 40-bit integers (ie our LLVM assembler use i40 types). It seems as every native type should be added as a Machine Value Type (MVT). However, it also seems to be required that each SimpleValueType enum in MVT has a bit-width that is a power of 2. Do any of you have ideas how to add support for

(Not sure if this exactly maps to “truncating store”, but I think it at least touches some of the subjects discussed in this thread) Our out-of-tree-target need several patches to get things working correctly for us. We have introduced i24 and i40 types in ValueTypes/MachineValueTypes (in addition to the normal pow-of-2 types). And we have vectors of those (v2i40, v4i40). And the byte size in our

They are starting to look complicated. The patch linked is interesting, perhaps v1 vectors are special cased. It shouldn't be too onerous to work out what one or two in tree back ends do by experimentation. Thanks again, it's great to have context beyond the source. On Fri, Sep 15, 2017 at 9:41 PM, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 9/15/2017 12:10 PM, Jon

On 9/25/2017 9:14 AM, Björn Pettersson A wrote: > > (Not sure if this exactly maps to “truncating store”, but I think it > at least touches some of the subjects discussed in this thread) > > Our out-of-tree-target need several patches to get things working > correctly for us. > > We have introduced i24 and i40 types in ValueTypes/MachineValueTypes > (in addition to

On Nov 22, 2008, at 7:48 AM, Wei wrote: > Do you mean MVT::getIntegerVT? Because I can not find > getExtendedIntegerVT in the llvm source codes. > I am excited seeing this function, however I have the following more > questions. See ValueTypes.h and ValueTypes.cpp. Also this example: @str = internal constant [4 x i8] c"%d\0A\00" define void @foo2(i24 %a, i24 %b) nounwind

Hello everybody, I have stumbled upon a test case (the attached module is a slightly reduced version) that shows extremely reduced performance on linux compared to windows when executed using LLVM's JIT. We narrowed the problem down to the actual code being generated, the source IR on both systems is the same. Try compiling the attached module: llc -O3 -filetype=asm -o BAD.s BAD.ll Under

---------- Forwarded message ---------- From: OvermindDL1 <overminddl1 at gmail.com> Date: Sat, Dec 5, 2009 at 8:12 PM Subject: Re: [LLVMdev] Fwd: Adding multiples-of-8 integer types to MVT To: ether zhhb <etherzhhb at gmail.com> On Sat, Dec 5, 2009 at 7:24 PM, ether zhhb <etherzhhb at gmail.com> wrote: > ya, when you targeting some backend like FPGA, you are able to meet a