similar to: [LLVMdev] PATCH: X86 calling convention cleanup

On 2008-01-01, at 20:05, Gordon Henriksen wrote: > The attachment supersedes the previous patch. It incorporates some > feedback from Anton and takes the next step of merging the largely > duplicated calling convention logic in X86ISelLowering. > > • LowerCCCArguments, LowerX86_64CCCArguments and > LowerFastCCArguments are merged and inlined directly into >

Hi all, The attachment supersedes the previous patch. It incorporates some feedback from Anton and takes the next step of merging the largely duplicated calling convention logic in X86ISelLowering. LowerCCCArguments, LowerX86_64CCCArguments and LowerFastCCArguments are merged and inlined directly into LowerFORMAL_ARGUMENTS. I moved LowerFORMAL_ARGUMENTS to the location where

On Mon, Apr 13, 2020 at 1:16 PM Jon Roelofs via llvm-dev < llvm-dev at lists.llvm.org> wrote: > As an update, after lots of fixes from a number of different people > (thanks everyone!), the current list of false-positives on `ninja > check-llvm` for the more stringent Gotcha A diagnostic is: > > LLVM :: Analysis/CostModel/X86/vselect-cost.ll > LLVM ::

Hi all, As previously mentioned on this list the Haskell compiler GHC has a new LLVM based back-end. The back-end needs a new calling convention to efficiently use LLVM and that is what this patch does, just for X86 at the moment. Breakdown: 1) Need actual calling convention Touches: - include/llvm/CallingConv.h - lib/Target/X86/X86CallingConv.td 2) Handling new calling

2014-12-15 13:00 GMT+01:00 Daniel Sanders <Daniel.Sanders at imgtec.com>: >> LLVM: CodeGen/Mips/cconv/arguments-struct.ll > > Do you have the verbose lit output for this test? > I ran it again in verbose mode, but there were no additional outputs. Cheers, Sebastian

On Mar 2, 2010, at 5:33 PM, David Terei wrote: > Hi all, > > As previously mentioned on this list the Haskell compiler GHC has a new LLVM based back-end. The back-end needs a new calling convention to efficiently use LLVM and that is what this patch does, just for X86 at the moment. Nice, > The GHC developers would love to get this included in LLVM so that we don't need to

OK, new patch attached. Hopefully in time for 2.7. Chris Lattner wrote: > 1) is the GHC calling conv intended to be target specific? If it is x86 specific, it should get an X86 prefix. If not, it should move up to be #10 after Cold. No its intended to be supported on any platforms that GHC is supported on, which is just x86 and SPARC at the moment. At the moment I've just done X86, will

> On 15.12.2014, at 15:45, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: > >> -----Original Message----- >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >> On Behalf Of Sebastian Dreßler >> Sent: 15 December 2014 14:08 >> Cc: Ben Pope; Nikola Smiljanic; llvmdev >> Subject: Re: [LLVMdev] 3.5.1 Testing Phase

You're not the only one Hans, my VMs have started crashing my host OS :) Fedora and OpenSUSE look good, binaries uploaded. On Sat, Dec 13, 2014 at 12:06 PM, Hans Wennborg <hans at chromium.org> wrote: > > On Thu, Dec 11, 2014 at 5:26 PM, Tom Stellard <tom at stellard.net> wrote: > > Hi, > > > > 3.5.1-rc1 has been tagged, so it is time to begin testing. We

Hi Evan, The commit http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20060327/033389.html broke CVS. The attached obvious patch fixes it. I don't have write access . So can someone commit this in ? ramana at zirakzigil:~/fsf/llvm/llvm/lib/Target/X86$ cvs diff -au X86ISelLowering.cpp Index: X86ISelLowering.cpp ===================================================================

Ignore the suggested fix in my earlier post. How about this? diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 20c81c3..b8ebf42 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1632,10 +1632,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, if (!Subtarget.is64Bit()) { // These

We should handle this a lot better after r34763 ~Craig On Mon, Nov 26, 2018 at 3:13 PM Craig Topper <craig.topper at gmail.com> wrote: > Here's a quick patch that fixes this. I don't know to avoid it in IR. I > haven't checked any other tests, but it does fix your case. I'll try to put > up a real phabricator tonight or tomorrow. > > diff --git

Most LLVM IR instructions have a result field, according to the Language Reference. I want to know, for all LLVM Instructions, is there an easy and consistent way to know if the current Inst has a result field? And if yes, what is the best way to obtain it? E.g.: <result> = add<ty> <op1>,<op2> /; yields {ty}:result / All ADD instruction will have a

rc1 did not exhibit this mismatch. A repeat of the rc2 build repeated the mismatch. I diff'd the disassembly between phase 2 and phase 3 and the difference is the same on both builds. The difference follows: # diff x86isel_p{2,3}.s 2c2 < Phase2/Release/llvmCore-8.0.0-rc2.obj/lib/Target/X86/CMakeFiles/LLVMX86CodeGen.dir/X86ISelLowering.cpp.o: file format elf64-x86-64 --- >

Hi Chuck, > Most LLVM IR instructions have a result field, according to the Language Reference. > > I want to know, for all LLVM Instructions, is there an easy and consistent way > to know if the current Inst has a result field? > And if yes, what is the best way to obtain it? the instruction is the result! So everywhere you though you needed to use Instruction->getResult(),

/Volumes/mrs5/net/llvm/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp: In member function 'llvm::SDOperand llvm::X86TargetLowering::LowerTRAMPOLINE(llvm::SDOperand, llvm::SelectionDAG&)': /Volumes/mrs5/net/llvm/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp: 5305: warning: dereferencing type-punned pointer will break strict- aliasing rules :-(

Hi, 3.5.1-rc1 has been tagged, so it is time to begin testing. We can always use more testers, so if you would like to volunteer, let me know. For those that are new to testing, please review the documentation for how validate a new release: http://llvm.org/docs/ReleaseProcess.html Remember that when we check for regressions we want to compare the test results of 3.5.1-rc1 with 3.5.0-final.

Yeah. I agree that "Chain operand is needed if the intrinsic is reading / writing memory.”, Just don’t know where and how to set it up. like intrinsic “int_x86_xtest: “ def int_x86_xtest : GCCBuiltin<"__builtin_ia32_xtest">, Intrinsic<[llvm_i32_ty], [], []>; “ "def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0,

Hi, LLVM made a change a few months ago and starting erroring out when a float is returned in x64 and SSE is disabled. This makes sense, really, since it's specified by the ABI that the return value must be put in a register you were told to disable, but it's breaking soft floats in Rust on x64. It seems there are two options: LLVM could break the ABI spec and have working soft floats on

Hi I want to replace all the return instructions in the program with pop <reg>; jmp <reg>. Should I use IRBuilder in LLVM IR level? I found that there is a IRBuilder::CreateIndirectBr Or Should I modify the code in lib/Target/X86/X86ISelLowering.cpp in backend ? I found that there is a X86TargetLowering::LowerCall Which is better? Thanks -------------- next part --------------