similar to: [LLVMdev] Re: AMD64

Does anybody know if there is some tool to convert from WHIRL to LLVM? maybe some project under development? a similar project? Thanks > > --- Duraid Madina <duraid at octopus.com.au> wrote: > > Date: Fri, 18 Mar 2005 12:45:54 +0900 > > From: Duraid Madina <duraid at octopus.com.au> > > To: ahs3 at fc.hp.com, LLVM Developers Mailing List <llvmdev at

On Sat, 05 Aug 2006 15:25:28 -0700, Reid Spencer wrote: > On Sat, 2006-08-05 at 14:45 -0400, Hendrik Boom wrote: >> The hardware requirements claim that there is no native code generation >> for the AMD 64. Is anyone working toward this? >> >> -- hendrik >> > Unfortunately, no. There is a scant beginning for x86_64 support, an > initial (read slow)

Hi, The attached patch contains the following changes: * X86InstrInfo.cpp: Synchronize a few places with the code in X86CodeEmitter.cpp * X86CodeEmitter.cpp: Avoid the longer SIB encoding on amd64 if it is not neeed. Zoltan -------------- next part -------------- An HTML attachment was scrubbed... URL:

Looks good. Thanks. Evan On May 1, 2009, at 8:40 AM, Zoltan Varga wrote: > Hi, > > The attached patch contains the following changes: > > * X86InstrInfo.cpp: Synchronize a few places with the code in > X86CodeEmitter.cpp > * X86CodeEmitter.cpp: Avoid the longer SIB encoding on amd64 if it > is not neeed. > > Zoltan >

Hi, The attached small path fixes X86InstrInfo::getMemModRMByteSize to be consistent with the emit code in X86CodeEmitter::emitMemModRMByte on amd64. Zoltan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090408/ad831982/attachment.html> -------------- next part -------------- A non-text

You are right, the machine I am on is a AMD Opteron. I could probably generate working code for x86, but I am testing the implications of using 64 bits integers. The four weeks is not really important, it's just that it would be nice to have really fast code to showcase. Something related to this: to test the effect of 64 bits integers I replace all reference of int by long in my .ll file.

Committed as revision 70929. Thanks. Evan On May 3, 2009, at 8:29 PM, vargaz wrote: > > Hi, > > If this looks ok, could somebody check it in ? > > thanks > > Zoltan > > > Evan Cheng-2 wrote: >> >> Looks good. Thanks. >> >> Evan >> >> On May 1, 2009, at 8:40 AM, Zoltan Varga wrote: >>

Hi, If this looks ok, could somebody check it in ? thanks Zoltan Evan Cheng-2 wrote: > > Looks good. Thanks. > > Evan > > On May 1, 2009, at 8:40 AM, Zoltan Varga wrote: > >> Hi, >> >> The attached patch contains the following changes: >> >> * X86InstrInfo.cpp: Synchronize a few places with the code

Hi Zoltan, The part that determines whether SIB byte is needed caused a lot of regressions last night (see Geryon-X86-64 etc.). I've reverted it for now. Please take a look. Thanks, Evan On May 4, 2009, at 3:49 PM, Evan Cheng wrote: > Committed as revision 70929. Thanks. > > Evan > > On May 3, 2009, at 8:29 PM, vargaz wrote: > >> >> Hi, >> >>

Hi, I can't reproduce these failures on my linux machine. The test machine seems to be running darwin. I suspect that the problem might be with RIP relative addressing, or with the encoding of R12/R13, but the code seems to handle the latter, since it checks for ESP/EBP which is the same as R12/R13. Zoltan On Tue, May 5, 2009 at 8:18 PM, Evan Cheng <evan.cheng at

Hi there, The IA64 architecture, which had its 'official' name changed to the "Itanium Processor Architecture", *is* supported by llc. I am pretty sure you are talking about the x86-64 architecture, which has also had its share of unfortunate name changes and is also known as "AMD64", "EM64T" and all sorts of things in between. x86-64 is *not* currently

Hi, It looks like the problem was with the RIP relative addressing. The original patch mistakenly removed the || DispForReloc part because I tough that the RIP relative addressing was done by the SIB encodings, but it is actually done by the shorter ones. The attached patch seems to work for me on linux and when simulating darwin by forcing some variables in X86TargetMachine.cpp to their darwin

On Thu, 2004-12-30 at 11:14, Francisco Puentes wrote: > Hi, everybody: > Hi Francisco > > I am a beginner with LLVM, in fact today was the first day that I use it. Welcome! > > I have several questions about LLVM: If you haven't already, a good place to start is the Getting Started Guide, at http://llvm.cs.uiuc.edu/docs/GettingStarted.html > Can I use LLVM to

Andrew Lenharth wrote: > On Fri, 2005-03-18 at 05:04 +0900, Duraid Madina wrote: >> - No varargs > > What are your issues here? Or are they simply at the "not implemented > so I don't know" stage? The two bugs I mentioned (no varargs, no alloca) are pretty much two sides of the same coin: I'm ignoring the IA64 stack frame layout (for no good reason), so

> The assert is at TargetLowering.cpp:138. > > Why is FP required? There's no particularly fundamental reason - while LLVM specifies a modest set of FP capabilities... > Most ARMs don't have an FPU. Should I add a fake > register class for MVT::f64? ...nothing will break if you just pretend f64 fits in your integer registers so long as you don't go anywhere near FP in

Hello Duraid, Duraid Madina wrote on Wednesday, 11 May 2005: >> I've just tried building CVS/HEAD of llvm using gcc 4.0.0 that I >> have installed to /opt/gcc > ... then you should either add /opt/gcc/lib to /etc/ld.so.conf and > rerun ldconfig, or add /opt/gcc/lib to your LD_LIBRARY_PATH . > However, GCC 4.x definitely has issues building LLVM, at least on > ia64. Oh,

On Fri, 2005-03-18 at 05:04 +0900, Duraid Madina wrote: > I've just checked in an IA64 backend to LLVM! Woo hoo! And There Was Much Rejoicing in IA64 Land :-). -- Ciao, al ---------------------------------------------------------------------- Al Stone Alter Ego: Linux & Open Source Lab Debian Developer Hewlett-Packard

Unfortunately, no. There is a scant beginning for x86_64 support, an initial (read slow) implementation of IA64, but nothing for AMD 64. I'm told that adding AMD 64 support could be done in 2-3 months (for someone familiar with LLVM Targets) if someone were to attempt it. Reid. On Sat, 2006-08-05 at 14:45 -0400, Hendrik Boom wrote: > The hardware requirements claim that there is no

Hi Vasanth, Can you be a little more precise about what you mean by "dynamic optimization"? In one sense, neither LLVM nor Pin are dynamic optimization tools per se - LLVM is more of a compiler(-building) suite while Pin is an instrumentation toolkit. > 1. I should be able to run all the Spec 2000 and Spec 95 floating point > and integer benchmarks. LLVM will do this - if it

On Fri, 2005-03-18 at 05:04 +0900, Duraid Madina wrote: > Hi everyone, > > I've just checked in an IA64 backend to LLVM! Be warned, it's pretty > rough right now. Here are some of the known defects: > > - No varargs What are your issues here? Or are they simply at the "not implemented so I don't know" stage? Namely, I am working on some varargs