llvm dev - Aug 2006 - [LLVMdev] a target must have floating point support?

> The assert is at TargetLowering.cpp:138.
>
> Why is FP required?
There's no particularly fundamental reason - while LLVM specifies a modest
set of FP capabilities...
> Most ARMs don't have an FPU. Should I add a fake
> register class for MVT::f64?
...nothing will break if you just pretend f64 fits in your integer
registers so long as you don't go anywhere near FP in your code. So just:

addRegisterClass(MVT::f64, <your chosen integer reg class>)

Also, if you *do* want to support (software) FP you should do that anyway,
then just lower FP operations to library calls and/or custom LLVM
sequences operating on your integer representation of floats.

HTH,

   Duraid

On Sun, 20 Aug 2006 duraid at octopus.com.au wrote:
>> Most ARMs don't have an FPU. Should I add a fake
>> register class for MVT::f64?
>
> ...nothing will break if you just pretend f64 fits in your integer
> registers so long as you don't go anywhere near FP in your code. So
just:
>
> addRegisterClass(MVT::f64, <your chosen integer reg class>)
>
> Also, if you *do* want to support (software) FP you should do that anyway,
> then just lower FP operations to library calls and/or custom LLVM
> sequences operating on your integer representation of floats.
Yep.  We don't support any targets that require software FP support, and 
I'm not very knowledgable about that area.  However, it would be very nice 
if the target-independent code did this lowering, so that the code 
could be shared across multiple targets.

-Chris

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