similar to: [LLVMdev] Operand constraints

Vladimir Prus wrote: > On my target, the multiplication can involve all general purpose registers, > but there's are still some restrictions: the first and the second operand > as well as the result must be in different registers, and neither register > can be gr7. How can I enforce this restriction on the register allocator? And the other side of the question is now to inform

Folks, I'm running into something which looks like a bug in linearscan allocator. Of course I can't be 100% sure it's not some unobvious mistake on my part, so I'd like to hear your opinion. First, I attach two files -- LLVM asm and the asm for my target. The problem with assembler is: on line 171 it uses register gr2, which is copied from gr6 above, on line 161. The only

On Tue, 22 Jun 2004, Vladimir Prus wrote: > First, I attach two files -- LLVM asm and the asm for my target. The problem > with assembler is: on line 171 it uses register gr2, which is copied from gr6 > above, on line 161. The only predecessor of this basic block is jump on line > 90. The problem is that gr6 is not initialized in the interval from the > function entry till the

Hello! Is there an (semi)automatic way to save registers used by a function? For example, on my target I have to store ar0-ar4 and gr0-gr4, gr5, gr6. For now I just emit huge prologue code to push them all to stack -- even if they are not modified at all. Is there a way to tell LLVM which registers must be stored, and have it automatically issue pushes/pops? I can live with current design,

On Wed, 2004-06-09 at 04:56, Vladimir Prus wrote: > Hello! > Is there an (semi)automatic way to save registers used by a function? For > example, on my target I have to store ar0-ar4 and gr0-gr4, gr5, gr6. For now > I just emit huge prologue code to push them all to stack -- even if they are > not modified at all. > > Is there a way to tell LLVM which registers must be

Alkis Evlogimenos wrote: > On Wed, 2004-06-09 at 04:56, Vladimir Prus wrote: > > Hello! > > Is there an (semi)automatic way to save registers used by a function? For > > example, on my target I have to store ar0-ar4 and gr0-gr4, gr5, gr6. For > > now I just emit huge prologue code to push them all to stack -- even if > > they are not modified at all. > > >

Hi everyone. I want to solve the following problem. I have a data.frame and I create a dotplot using lattice. Then I want to use the grid-package to create a combined graphic which contains the dotplot as well as a textplot() (using package gplots) of the data.frame next to the dotplot. Example code: library(lattice) library(grid) library(gplots) xx <- data.frame(f=factor(rep(1:5, each=5)),

Chris Lattner wrote: > On Tue, 22 Jun 2004, Vladimir Prus wrote: > > First, I attach two files -- LLVM asm and the asm for my target. The > > problem with assembler is: on line 171 it uses register gr2, which is > > copied from gr6 above, on line 161. The only predecessor of this basic > > block is jump on line 90. The problem is that gr6 is not initialized in > >

http://bugzilla.mindrot.org/show_bug.cgi?id=938 Summary: "AllowGroups" option and secondary user's groups limit Product: Portable OpenSSH Version: 3.9p1 Platform: ix86 OS/Version: Linux Status: NEW Severity: major Priority: P2 Component: PAM support AssignedTo: openssh-bugs at

I've tried to implement the isMoveInstr method from TargetInstrInfo class, and the register allocator immediately started to crash, in: #4 0x40e88787 in llvm::LiveIntervals::joinIntervals (this=0x80630b0) at ../lib/CodeGen/LiveIntervals.cpp:493 493 assert(r2iA != r2iMap_.end()); The instruction it crashes is: (gdb) p $4.dump() %reg1056 = move %gr7 And gr7 is

On Wed, 9 Jun 2004, Vladimir Prus wrote: > Chris Lattner wrote: > > > Thanks, this works! I don't yet understand why spill code is needed there > > > at all, but I'll return to that when I have branches working correctly. > > > > I'm not sure either. Can you send the code before and after register > > allocation? > > Attached. Okay, yeah

Chris Lattner wrote: > > Thanks, this works! I don't yet understand why spill code is needed there > > at all, but I'll return to that when I have branches working correctly. > > I'm not sure either. Can you send the code before and after register > allocation? Attached. > You might also try -regalloc=linearscan, as the default > allocator is, uhhh,

Dear all, I get an error message when I use polr() in MASS. These are my data: skugg grupp frekv 4 1 gr3 0 5 2 gr3 3 6 3 gr3 6 10 1 gr5 1 11 2 gr5 12 12 3 gr5 1 > > summary(polr(skugg ~ grupp, weights=frekv, data= skugg.cpy1.dat)) Error in optim(start, fmin, gmin, method = "BFGS", hessian = Hess, ...) :

Dear R-users, I would like to maximize the function g above which depends on 4 parameters (2 vectors, 1 real number, and 1 matrix) using optim() and BFGS method. Here is my code: # fonction to maximize g=function(x) { x1 = x[1:ncol(X)] x2 = x[(ncol(X)+1)] x3 = matrix(x[(ncol(X)+2):(ncol(X)+1+ncol(X)*ncol(Y))],nrow=ncol(X),ncol=ncol(Y)) x4 = x[(ncol(X)+1+ncol(X)*ncol(Y)+1):length(x)]

Hi, looking at the fresh CVS state I see: class Register<string n> : RegisterBase<n> { list<RegisterBase> Aliases = []; } while previously the Register class did not require any parameters. The change log is just: * Target.td: Revamp the Register class, and allow the use of the RegisterGroup class to specify aliases directly in register definitions. and I

On Wed, 9 Jun 2004, Vladimir Prus wrote: > > I assume that the two unconditional gotos are just test code, right? If > > not, the second one is dead. > > Yes, in the final form there will be "iflt" instruction before the first goto, > making it conditional. Ah, ok :) > > > The code after "goto" is disturbing. It looks like spill code, but

On Wed, 2004-06-09 at 05:26, Vladimir Prus wrote: > Alkis Evlogimenos wrote: > > On Wed, 2004-06-09 at 04:56, Vladimir Prus wrote: > > > Hello! > > > Is there an (semi)automatic way to save registers used by a function? For > > > example, on my target I have to store ar0-ar4 and gr0-gr4, gr5, gr6. For > > > now I just emit huge prologue code to push

On Thu, 2004-07-01 at 09:26, Vladimir Prus wrote: > I've tried to implement the isMoveInstr method from TargetInstrInfo class, and > the register allocator immediately started to crash, in: > > #4 0x40e88787 in llvm::LiveIntervals::joinIntervals (this=0x80630b0) > at ../lib/CodeGen/LiveIntervals.cpp:493 > 493 assert(r2iA != r2iMap_.end()); >

Chris Lattner wrote: > On Tue, 8 Jun 2004, Vladimir Prus wrote: > > While adding support for branch instructions in my backend, I run into a > > trouble. The code to handle branches looks like: > > The machine code after instruction selection is: > > > > entry (0x8681458): > > %reg1024 = load <fi#-1> > > %reg1025 = load

On Wed, Jan 16, 2013 at 12:04:52PM -0500, Stephen Checkoway wrote: > > On Jan 16, 2013, at 10:07 AM, Brad Smith <brad at comstyle.com> wrote: > > > I was wondering if someone with more familiarity with MC > > on X86 could consider looking into adding support for > > the hyphenated versions of the VIA Padlock instructions? > > > Take a look at