similar to: Live Register Spilling

Hi Matthias, Sorry for the late reply. Yes, you are correct, I do have optnone attribute on my function. I did pass -O0 to the tools. For your information, my invocations are as below: clang --target=mips-unknown-linux -mips32 test.c -emit-llvm -S llc -O0 -march=mips -mcpu=mips32 test.ll -o test.s Based on the generated .ll file, there is optnone attribute on the function, i

Running llc with '-verify-machineinstrs' may tell you which instruction break the SSA form. Ruiling From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of jin chuan see via llvm-dev Sent: Monday, September 11, 2017 10:02 AM To: Matthias Braun <mbraun at apple.com> Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Live Register Spilling Sorry about the

> On Sep 13, 2017, at 9:03 PM, jin chuan see via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi All, > > Thanks for the reply. I managed to identify and fixed a few errors in my implementation. > > However, there are a few errors that i am not sure what is it indicating. > For starters, i think i should explain what i am trying to achieve. > > I am

Hello, I've been trying to figure out how to reproduce the results of a single clang -O3 compilation to a binary with a multi-step process using opt. Specifically I have: clang -O3 foo.c -o foo.exe which I want to replicate with: clang -O0 -c -emit-llvm foo.c opt -O3 foo.bc -o foo_o.bc clang foo_o.bc -o foo.exe Any hints / suggestions on what additional flags I need to produce the same

Awesome, thanks! I'd like to have the last step (llc in your example) not perform additional optimization passes, such as O3, and simply use the O3 pass from opt in the previous line. Do you happen to know if I should use 'llc -O0 foo_o.bc -o foo.exe' instead to achieve this? On Thu, Jul 2, 2020 at 6:35 PM Mehdi AMINI <joker.eph at gmail.com> wrote: > > > On Thu,

We'll be doing something similar for our OpenVMS port.  Right now I'm using "AsmStreamer->GetCommentOS()" and writing to the stream at the assembler level but that gets aligned on a right-side column (the column is hardcoded) and you have to be in verbose mode.  So if you come up with something or have a quick design, post it so perhaps we can leverage each other's work. 

When I am constructing sequences of instructions during custom lowering, I would like to be able to also add a comment that appears in the generated assembly with '-S -fverbose-asm'. There is a large set of 'add*' functions to attach additional information to the MI, but I don't see one for adding comments. Is there a method I can call to attach an arbitrary string

Dear Prof: My name is Chuan.I from Malaysia.I am a beginner for R.I need favor for Prof. This is my data: y<-c(52,55,61,66,70,61,64,73,63,59,55,90,109,85,69,72,62,59,68,113,144,104,66,73,63,58,71,122,154,106,70,69,67,61,68,104,126,88,68,70,79,65,60,70,77,68,58,75,85,71,64,59,55,61,65,83,87,79,69,68,65,76,78,94) and I form it into matrix as below: [,1] [,2] [,3] [,4] [,5] [,6] [,7] [,8]

Does anybody have any tips for generating spills/reloads for large non-vector registers? I'm working on a back end for a DSP architecture that has accumulator registers that are too large to be spilled or reloaded with a single instruction. All of their bits can be accessed in word-size chunks via three sub-registers (low, high, and ext). So loading or storing one requires three instructions:

I'm having trouble with virtual registers/register allocation in my back-end. Basically the FastRegAlloc pass is generating calls to storeToStackSlot and loadFromStackSlot, in which we build new machine instructions, which are then _not_ processed by the reg allocator. I understand that BuildMI is changing the list of MachInst. that the allocator is iterating over, but we need to have a new

This shouldn't have parsed. movq (%gs), %r14 That's trying to use%gs as a base register which isn't valid. GNU assembler rejects it. And coincidentally llvm-mc started rejecting it on trunk late last week. That's probably why it printed as %ebp. I don't know if there is an instruction to read the base of %gs directly. Maybe rdgsbase, but that's only available on Ivy

Hi Bill, I am using the following version of BuildMI : MachineInstrBuilder BuildMI(MachineFunction &MF, const TargetInstrDesc &TID, unsigned DestReg) I do the following : void createInstrs(std::vector<MachineInstr *>& ilist) { Machine Instr *mi; mi = BuildMI(MF, someTID, somereg);

There is no generic mechanism as far as I know. You can look at AsmPrinter.cpp/emitComments() to see what situations trigger comments at the moment. - Matthias > On Feb 3, 2018, at 4:40 AM, Martin J. O'Riordan via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > When I am constructing sequences of instructions during custom lowering, I would like to be able to also add a

Dear All. I am Chuan. I am beginner for R.I facing some problem in remove element from vector.I have a vector with size 238 element as follow(a part) [1] 0 18 24 33 44..................................[238] 255 Let the vector label as "x",I want remove element "0" and "255".I try use such function: x[x>0 & x<255] However, I am fail since same results

Hello, I want to add assembly instructions at certain points in a function. This is X86 specific. So I am working in the lib/Target/X86 folder. I create a `MachineFunctionPass` in that folder. I register it in the X86TargetMachine.cpp in addPreEmitPass(). I use BuildMI to insert my own assembly instructions in the MachineFunctionPass. This works and my assembly instructions are inserted at

Hello Dean, I looked at the XRay Instrumentation. That's a nice engineering effort. I am sure you had your motivation to do this in CodeGen just like I wanted to do. I don't understand all of your code but I get the idea that you are adjusting the alignment with explicit bytes and no-op instructions. My problem is also very much related to yours where my stack pointer ($rsp) alignment

Hi LLVM Dev, I have an old problem that I've wanted to clean-up for some time. Our chip has gone through a number of iterations in the past few years, but with each revision there have been changes to some of the mnemonics for instructions. These are mostly very simple, for example we had a 32-bit load from memory instruction named 'LD32' in one version of the chip, but for a

Hello, For the following test case, reg.c #include <stdio.h> int getinput() { static int u=10; return u++; } int main() { int a,b,c,d,e,f,g; a=getinput(); b=getinput(); c=getinput(); d=getinput(); e=getinput(); f=getinput(); g=getinput(); printf("%d %d %d %d %d %d %d\n",a,b,c,d,e,f,g); a=b=c=d=e=f=g=0; return 0; } *1.

Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird. For an add, when I use BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm). if reg is R0 - R7, everything is fine: I would get something like adds r1, 4 But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get

I just changed the default register allocator for -O0 builds to the fast allocator. This means that the local register allocator is not used anymore, and since it does more or less the same as the fast allocator, there is no reason to keep it around. I am going to delete it in a week or two. If you are using the local register allocator, please try switching to the fast allocator and report any