similar to: Wrong description about getelementptr arguments?

> Documentation's a bit stale - it'd probably be enlightening/helpful to > look at some real world examples, such as: > > %arrayidx = getelementptr inbounds i32*, i32** %0, i64 3 > > So the first argument (i32*) is a type, currently it's the same type as > the type that the second argument points to (or, in the case of a vector > gep, it's the type of the

Hi, I wonder whether the current version of LLVM supports separate compilation and linking of device code, i.e., is there a flag analogous to nvcc's --relocatable-device-code flag? If not, is there any plan to support this? Thanks! Yuanfeng Peng -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, all I found in some cases the int variable get promoted to i64, although I think it should i32. I use the online demo (http://llvm.org/demo). And below is the test case. ------------- test case ------------- int test(int x[], int y[], int n) { int i = 0; int sum = 0; for ( ; i < n; i++) { sum += x[i] * y[i]; } return sum; } ------------------------------------- No

Hi Mats, It's private backend. I will try describing what I am dealing with. struct S { unsigned int a : 8; unsigned int b : 8; unsigned int c : 8; unsigned int d : 8; unsigned int e; } We want to read S->b for example. The size of struct S is 64 bits, and seems LLVM treats it as i64. Below is the IR corresponding to S->b, IIRC. %0 = load

> On Jun 16, 2017, at 2:43 PM, 陳韋任 via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > 2017-06-17 4:36 GMT+08:00 upcfrost <upcfrost at gmail.com <mailto:upcfrost at gmail.com>>: > Hi, > > Same here, my backend only has 64bit load/store. But i still use 64bit virt regs and expand/declare missing instructions by myself. > > I'll try

Hi, Same here, my backend only has 64bit load/store. But i still use 64bit virt regs and expand/declare missing instructions by myself.  I'll try looking into sparc backend, thanks. Also, only after writing this post I found a bunch of built-in transforms. Still trying to understand how to use those. By the way, constraint-wise (alignment), is there any difference between virt regclass and

On 6/15/2017 11:13 PM, Ehsan Amiri wrote: > > Forgot to reply to all > > Hi Eli > >> We want to read S->b for example. The size of struct S is 64 >> bits, and seems LLVM treats it as i64. >> Below is the IR corresponding to S->b, IIRC. >> >> %0 = load i64, *i64 ptr, align 4; >> %1 = %0 lshr 8;

Also you might need to check use PostRASchedulerList or PostMachineScheduler, PostRASchedulerList is considered deprecated as mentioned in [1]. [1] http://lists.llvm.org/pipermail/llvm-dev/2017-April/112348.html HTH, chenwj 2017-06-10 4:03 GMT+08:00 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw>: > Not saying I am totally understand how thing works, but I think you're > misleading >

Hi all, I think it's Gentoo's bug, but I want to know if anyone has the same issue here. I am compiling LLVM trunk on Gentoo (gcc 4.5.2), and I get error message below, --- make[4]: Entering directory `/nfs_home/chenwj/llvm-3.1/svn/build/tools/clang/lib/Frontend' llvm[4]: Compiling InitHeaderSearch.cpp for Release+Asserts build

Hi Justin, I believe the PTX section in the link below need some love, updating "lib/Target/PTX" to "lib/Target/NVPTX" for example. Would you like to take a look? http://llvm.org/docs/CodeGenerator.html#the-ptx-backend Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667

Hi 陳韋任, Sorry for the late response. On Apr 21, 2012, at 8:03 PM, 陳韋任 wrote: > I have a native compile and the result seems better... You can compare > the result of cross compile [1] and the native compile [2]. > > Any though? > I'm not particularly happy about the failures here. We need to get to the bottom of them. In the previous email, you tried setting CFLAGS and

Hi, I'm trying to write an LLVM backend for Epiphany arch, and I wonder if someone can give me some advice on how to implement load/store optimization. The CPU itself is 32-bit, but it supports wider 64-bit loads and store. So the basic idea is to make use of those by combining narrow ones. I've checked how it is done in AArch64 and Hexagon, and my current code is very close to the

Thanks for the info, Philip. I will update the LLVM Programmer’s Manual first. Regards, chenwj Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj 2017-04-02 18:11 GMT+08:00 Philip Pfaffe <philip.pfaffe at gmail.com>: > Hi chenwj, > > http://llvm.org/doxygen/Statistic_8h_source.html is the correct one. The > other two are remnants from older doxygen deployments.

Hi weiren, Thanks for your suggestion! Yes, I am trying to do this "nested flattening". It seems that I need a post-dominator tree-based algorithm to flatten the nested loops from the innermost to the outermost, level by level. Is there any feature already existed in LLVM tools? Or similar? On Sun, Oct 22, 2017 at 2:31 AM, 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw> wrote: > If

Hi All, I have two trivial patches waiting for review. - https://reviews.llvm.org/D33281 - https://reviews.llvm.org/D32929 Anyone? :-) Regards, chenwj -- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj -------------- next part -------------- An HTML attachment was scrubbed... URL:

> In consideration of those codes in XXXAsmPrinter class which print out > MachineInstr in .s format, I tend to think they are old codes that > might be obsolete and will be replaced with MC layer implementation, > but I am not sure. How about sending a patch which remove those obsolete code, and let others give comment? Cheers, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab,

Thanks :) From: 陳韋任 [mailto:chenwj.cs97g at g2.nctu.edu.tw] Sent: 14 April 2017 12:53 To: Martin J. O'Riordan <martin.oriordan at movidius.com> Cc: LLVM Developers <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] Options for timing passes in LLVM? Refer to `llc` document [1], it would be `--time-passes`. [1] http://llvm.org/docs/CommandGuide/llc.html HTH,

Hi Bekket, I don't see any use case in the codebase adding clEnumValEnd at the end of list (for example, [1]), I also don't see there is clEnumValEnd. Do I miss something here? [1] http://llvm.org/doxygen/DwarfDebug_8cpp_source.html Regards, chenwj 2017-06-06 9:53 GMT+08:00 Bekket McClane via llvm-dev < llvm-dev at lists.llvm.org>: > Hi, > > Can anyone help reviewing

Hi All, The description of ScheduleDAGMILive [1] says: ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure. Does the live interval and register pressure part of ScheduleDAGMILive mean the subclass of ScheduleDAGMILive is a pre-RA scheduler? I assume the post-RA scheduler no need to take

Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing