similar to: Chaining and grouping

Hi, Does anybody know how codebooks are generated in OggVorbis encoder? We are porting oggorbis encoder on embedded platform for which VQ codebook memory is hugeeee to imagine. How can we reduce that? Can we do VQ with less codebooks and if yes how? If any help available? Parul Embedded Engineer Einfochips Ltd

We are working on OggVorbis encoder. In the porting effort we are trying to convert it to fixed point code (both 32 and 24 bit fixed point). Now the issue is how we do the testing. What should be the criteria for our testing. Does anybody has any idea how compliance testing (i.e. some objective tests) is done at encoder side? What is the criteria of testing at the encoder side? If anybody

For testing the encoder i needed test vectors. thanks for the links send by members. Those links are useful, but contain test vectors corresponding to 44 KHz only. Does anybody has any idea where i can find test vectors of other sampling rates i.e. 48 KHz, 32 KHz, 16 KHz, 11 Khz, 8 KHz. ? Thanks, Parul Embedded engineer Einfochips

Hi, We are working on Oggvorbis encoder porting on embedded platform. Where can we find good test vectors (wav files) for testing OggVorbis encoder? Does anybody have any idea. Parul Embedded Engineer Einfochips Ltd

Hi, Have anybody worked on converting OggVorbis encoder floating point code to fixed point (32 bit or 24 bit). How do you handle _vp_noisemask in that case where precision goes upto 40 bits. Any help available? Parul Embedded Engineer Einfochips Ltd

I have a question: In the pattern below from X86 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\tdst", [(set GR8:$dst, (add GR8:$src, 1))]>; Since we are emitting only "inc $dst", What makes sure that the $src and $dst are same register? - Sanjiv

sanjiv gupta wrote: > I have a question: > In the pattern below from X86 > > def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), > "inc{b}\tdst", > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Since we are emitting only "inc $dst", > What makes sure that the $src and $dst are same register? > > - Sanjiv It's enclosed

I have some instructions that use a register as both an input and as the output. Is there a way to specify this constraint in the InstrInfo.td or will this have to be custom selected/lowered? Thanks -- Christopher Lamb christopher.lamb at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, I wanted to let you know that I have just made available the sources to the ogg + vorbis implementation in haXe, which I've been working on for last couple of weeks. The code compiles to an swf file playable in Flash Player 10. A demo of a simple player implementation (latest Flash 10 required): http://people.xiph.org/~arek/pg/hx/test.html and the sources, in a bzr branch, currently

Hi, I wanted to let you know that I have just made available the sources to the ogg + vorbis implementation in haXe, which I've been working on for last couple of weeks. The code compiles to an swf file playable in Flash Player 10. A demo of a simple player implementation (latest Flash 10 required): http://people.xiph.org/~arek/pg/hx/test.html and the sources, in a bzr branch, currently

Hello. I write backend for Z80 cpu and I have some trouble with lowering load/store nodes to different machine opcodes. Some target instructions work with specified registers (not all registers in RegisterClass). Often it's one or two registers. I don't understand how use ComplexPattern in this case. But if I don't use ComplexPattern I'll have other problems - not all

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the

I see in the x86 InstInfo.td the following for the INC instructions: def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", [(set GR8:$dst, (add GR8:$src, 1))]>; Which seem to have the same restriction that I'm trying to implement, but I don't understand how this ensures that $src and $dst are the same register. -- Christopher Lamb

On Thu, 1 Mar 2007, Christopher Lamb wrote: > I see in the x86 InstInfo.td the following for the INC instructions: > > def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Which seem to have the same restriction that I'm trying to implement, > but I don't understand how this

On Tue, 2008-09-23 at 13:33 +0100, Richard Osborne wrote: > sanjiv gupta wrote: > > I have a question: > > In the pattern below from X86 > > > > def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), > > "inc{b}\tdst", > > [(set GR8:$dst, (add GR8:$src, 1))]>; > > > > Since we are emitting only "inc $dst",

Dear all, As the next version of XiphQT is mostly ready, I thought it could use some more wide pre-release testing. The major change since last release is the addition of Ogg exporter and Vorbis and Theora encoders. Any feedback on how this new functionality performs (or doesn't!) with audio/video editing/producing software will really help. Also, comments and suggestions on the work of

Dear all, As the next version of XiphQT is mostly ready, I thought it could use some more wide pre-release testing. The major change since last release is the addition of Ogg exporter and Vorbis and Theora encoders. Any feedback on how this new functionality performs (or doesn't!) with audio/video editing/producing software will really help. Also, comments and suggestions on the work of

Dear all, As the next version of XiphQT is mostly ready, I thought it could use some more wide pre-release testing. The major change since last release is the addition of Ogg exporter and Vorbis and Theora encoders. Any feedback on how this new functionality performs (or doesn't!) with audio/video editing/producing software will really help. Also, comments and suggestions on the work of

Hi, This patch fixes outs/ins of MOV16mr instruction of X86. Thanks. diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index e9a0431..f5b2064 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),

On Jun 3, 2011, at 2:59 AM, Galanov, Sergey wrote: > Hi, Bill and Jakob. > > I don't quite understand. I am talking about CMOV_GR* instructions which are conservatively marked as clobbering EFLAGS in X86InstrCompiler.td. Doesn't that mean there cannot be any use of EFLAGS in subsequent instructions before it is defined by some other instruction? > > I also don't