similar to: vorbis-tools-1.1.1 build mechanism stubbornly refuses to build with FLAC, ogg123, speex

Displaying 20 results from an estimated 4000 matches similar to: "vorbis-tools-1.1.1 build mechanism stubbornly refuses to build with FLAC, ogg123, speex"

2007 Nov 25
1
vorbis-tools-1.1.1 build fails during linking
Hello All, even though 'configure' for vorbis-tools-1.1.1 is OK 'make' fails - please see the command line and error messages below. Aby ideas why this happens ? Thanks, Sergei. The failing command line and error messages: 99 gcc -O20 -ffast-math -fsigned-char -o oggenc oggenc.o audio.o encode.o platform.o resample.o
2006 Dec 08
2
Fwd: vorbis-tools-1.1.1 build mechanism stubbornly refuses to build with FLAC, ogg123, speex
Anybody ? Note: forwarded message attached. Applications From Scratch: http://appsfromscratch.berlios.de/ ____________________________________________________________________________________ Need a quick answer? Get one in minutes from people who know. Ask your question on www.Answers.yahoo.com -------------- next part -------------- An embedded message was scrubbed... From: Sergei
2005 Dec 05
2
Re: [users] CentOS 4.2 dag repo problem.
Hello, It would be nice if we could get a full list of packages which have a wrong sha1 checksum. I don't have the bandwidth for a full mirror of all of Dag's rpms and i also don't have shell access to such a mirror. So a small request for a mirror admin: The following checks the files repodata/*.xml.gz against the sha1 sums in repomd.xml and checks the RPMS/*.rpm files against
2014 Jun 13
2
[LLVMdev] Looking for a fix to memory leak in DWARF support
Eric, Let me clarify it a bit... without type uniqueing for LTO + debug will I have a highly inefficient IR representation or incorrect debug info? If debug info for LTO is known to be non-useful or ambiguous or flat wrong - there is no point in fixing its emission... or will it still be practical and if I manage to improve it somewhat the customer will still have some value-add by using it?
2013 Jan 29
1
[LLVMdev] Apparent indeterminism in PreVerifier
Is there a test case that you can share ? On Jan 29, 2013, at 9:24 AM, Sergei Larin <slarin at codeaurora.org> wrote: > Nadav, > > Thanks for the quick response. By now I am convinced that the given loop > ends up vectorized with enough difference to cause bad things later on, but > I have not found the exact cause yet. To continue with my work I'll have to >
2014 Jun 13
2
[LLVMdev] Looking for a fix to memory leak in DWARF support
Thanks Eric, They are doing LTO build but with some custom modifications (think a library at a time as opposed to a whole program). I must admit, it is a rather large application as well, so as expected, any inefficiencies are multiplied greatly. >From little that I have seen so far, it looks like debug metadata for an IR object linger behind once the object itself is eliminated (optimized).
2012 Mar 29
0
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
Tom, I do not have your call stack, but packetizer calls ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is the first time you use the new MI sched infrastructure (like your target has not implemented misched yet) there might be some work needed to implement couple target hooks. isSchedulingBoundary is one of them. Also try to disable that assert and see what happens. It
2013 Jan 29
0
[LLVMdev] Apparent indeterminism in PreVerifier
Nadav, Thanks for the quick response. By now I am convinced that the given loop ends up vectorized with enough difference to cause bad things later on, but I have not found the exact cause yet. To continue with my work I'll have to simply turn off vectorization for now, but I will come back and investigate. Again, there is some indeterminism in order of PHIs processing somewhere. I'll
2012 Aug 13
0
[LLVMdev] MI bundle liveness attributes
Andy, Yes, this is what Arnold has suggested also, and from this point it looks like it should work, but it will require parsing the bundle every time we care to know whether this is a real use or a conditional def. This might become awkward... but I guess I should provide a better use case to prove my point. Sergei -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. >
2002 Nov 25
0
[Announce]OpenCDK 0.3.3
Current Version: 0.3.3 (latest devel 0.3.4-cvs) License: GPL Author: Timo Schulz <twoaday@freakmail.de> Available from: http://www.winpt.org/opencdk.html Hi, this is the first public announcement for OpenCDK. It is a library to provide some basic parts of the OpenPGP Message Format (RFC2440). First the library was planned for key conversation in GnuTLS and other applications which
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
Lang, I think I am getting closer to understanding this. The findLastUseBefore() should probably look something like this: // Return the last use of reg between NewIdx and OldIdx. SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) { SlotIndex LastUse = NewIdx; if (TargetRegisterInfo::isPhysicalRegister(Reg)) { for (MCRegUnitRootIterator Roots(Reg,
2012 Jun 07
0
[LLVMdev] Instruction bundles before RA: Rematerialization
Jakob, Please see my comments below. Hope this helps. Sergei -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Thursday, June 07, 2012 1:02 PM To: Sergei Larin Cc: 'Ivan Llopard'; 'LLVM Developers Mailing List' Subject: Re: [LLVMdev] Instruction bundles before RA: Rematerialization
2011 Nov 14
0
[LLVMdev] alias analysis in ScheduleDagInstr class
We observed exact same problem, and I did put in place a mechanism to recognize and break such false dependencies right before pre-RA scheduler (in DAG->DAG lowering), but the immediate observed effect for our back end was performance reduction, since none of the current schedulers were capable of dealing with newly presented parallelism in BB (resulted in high reg pressure and
2012 Aug 13
0
[LLVMdev] VLIW code generation for LLVM backend
But we are really striving to change it fast :) Dan, My comparative point was that LLVM has a greater potential to accommodate VLIW going forward than GCC does at this point. Would you agree to that? Sergei -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > From: Dan Gohman [mailto:gohman at apple.com] > Sent: Friday, August 10,
2012 Mar 29
2
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
On Thu, Mar 29, 2012 at 01:50:58PM -0500, Sergei Larin wrote: > Tom, > > What is in your isSchedulingBoundary? If it contains isLabel you might > need to disable that assert: > > assert(!MI->isTerminator() && !MI->isLabel() && > "Cannot schedule terminators or labels!"); > > Sergei Larin > > -- > Qualcomm
2012 Jun 08
0
[LLVMdev] Instruction bundles before RA: Rematerialization
Hi again! On 08/06/2012 17:11, Ivan Llopard wrote: > Hi Sergei, Jakob, > > Thanks for your comments ! > > On 07/06/2012 20:41, Sergei Larin wrote: >> >> Jakob, >> >> Please see my comments below. Hope this helps. >> >> Sergei >> >> -- >> >> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. >>
2012 May 11
6
[LLVMdev] Scheduler Roadmap
Dave, Thank you for your interest. Please see my replies below. Sorry that my terminology is not as crisp as Andy's, but I think you can see what I mean. Sergei -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > From: dag at cray.com [mailto:dag at cray.com] > Sent: Friday, May 11, 2012 12:14 PM > To: Sergei Larin > Cc:
2016 Feb 12
3
CloneFunction during LTO leads to seg fault?
In general I use DebugInfoFinder and clear out Metadata if GV in null or GV->isDeclaration(). If there is any interest, I can post that patch... Sergei --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > -----Original Message----- > From: Tobias Edler von Koch [mailto:tobias at codeaurora.org] > Sent: Friday, February 12, 2016
2013 Jan 29
2
[LLVMdev] Apparent indeterminism in PreVerifier
Hi Sergei, "addRuntimeCheck" inserts code that checks that two or more arrays are disjoint. I looked at the code and it looks fine. We generate PHIs in the order that they appear in a vector. The values are inserted in 'canVectorizeMemory', which also looks fine. Please let me know if you think I missed something. Thanks, Nadav On Jan 29, 2013, at 8:48 AM, Sergei Larin
2012 Jun 08
3
[LLVMdev] Instruction bundles before RA: Rematerialization
Hi Sergei, Jakob, Thanks for your comments ! On 07/06/2012 20:41, Sergei Larin wrote: > > Jakob, > > Please see my comments below. Hope this helps. > > Sergei > > -- > > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > > *From:*Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] > *Sent:* Thursday, June 07, 2012 1:02 PM > *To:* Sergei