similar to: FPGA implementation in the camera

Displaying 20 results from an estimated 4000 matches similar to: "FPGA implementation in the camera"

2004 Nov 17
4
FPGA implementation
Andrey Fillipov posted the following update at his sourceforge website on 11/16/04. "Coded and simulated the DC predictor module - hope the Theora description I used matches the actual codec :-) Also modified the modules released earlier to support non-coded blocks. For the DCT/IDCT I tried to reduce the power consuption by minimizing switching of the registers and counters when the
2011 Mar 22
0
FPGA implementation in the camera
Here http://lists.xiph.org/pipermail/theora/2004-September/000619.html Andrey describe encoder structure, this like: "I see the following structure of the compressor implemented in the FPGA (Xilinx Spartan 3 1000K gates): 1. Data from the external frame buffer (FB) memory goes to the Bayer-to-YCbCr (4:2:0) converter in overlapping 20x20 tiles that produce 6 8x8 blocks (one macroblock) on the
2011 Mar 22
5
FPGA encode stages flow diagram
Good day! I create diagram of encoder process. Using it i create implementation of encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing stages? Here is blog http://developer-fpga.blogspot.com/ Here is picture of encoding stage 1 https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg Here is picture of encoding stage 2
2005 Mar 08
6
FPGA implementation/ players speed?
Today I've got first video clips made by the camera and compressed "on the fly" - 1280x1024x30fps. Image quality is far from perfect - I don't have yet any way to preview images, and a single acquisition still requires a bunch of commands. So I'm really close to have a camera that will be able to serve the Ogg/Theora streams, now but will it be possible to play it on a PC? I
2021 Dec 02
1
NHW Project development
Raphael, Some 15 years ago I implemented limited functionality Theora in our cameras FPGA (it took me 6 month of hard labor), and then gave up - it is a very crowded space and it is difficult to compete with more advanced codecs. And for our other work we anyway need almost raw image data, so we are using JPEG-based JP4 format (https://community.elphel.com/jp4) that we originally developed for
2004 Nov 03
0
implementation in hardware
Andrey Filippov reports at his sourceforge website that he is 50% of the way towards the implementation of ogg theora in a FPGA, and has a goal of reaching 100% (leaving out motion compensation) by Dec. 14, 2004. These are some of the tasks he has completed most recently: Added 8-point forward DCT following the algorithm suggested in Theora specs. 2004-10-31 22:17 Created 2-d IDCT according
2004 Nov 03
0
implementation in hardware
Andrey Filippov reports at his sourceforge website that he is 50% of the way towards the implementation of ogg theora in a FPGA, and has a goal of reaching 100% (leaving out motion compensation) by Dec. 14, 2004. These are some of the tasks he has completed most recently: Added 8-point forward DCT following the algorithm suggested in Theora specs. 2004-10-31 22:17 Created 2-d IDCT according
2007 May 09
2
Next step of Hardware Theora
Hello, First of all, I would like to say that my work that I wrote in the other email would be to do in hardware the functions: CopyRecon, LoopFilter and UpdateUMVBorder. These are modules that Leonardo had made, but it wasn't ok in FPGA. When I had a chat with Leonardo we were thinking in rewrite these module for to do this running in FPGA (to debug in a Hardware level is much more
2008 Aug 15
6
handheld theora video camera wish list
What would your wish list be for a handheld theora video camera? 640x480 25fps/30fps 320x240 25fps/30fps Record to a memory card (SD) Lan / WIFI support (auto/manual upload of file on memory card) Live streaming (icecast like) Videoconferencing support Voip (sip) speex audio I am bouncing the idea around of developing a handheld video camera designed for mobile video streaming Win a
2021 Dec 02
1
NHW Project development
Hi Andrey, Thank you for your answer.Actually, NHW is very low-power so I think it could be geared toward any hardware.But actually I don't have hardware skills, so NHW is not a real hardware project for now maybe? I agree with you that it is extremely difficult (for me) to build a community around NHW, I'm certainly very bad/underskilled at it.Any help is welcome! Cheers, Raphael Le
2011 Mar 18
3
alghorithm of working encoder in libtheora
Hi, Is somewhere alghorithm description of encoder process implemented in libtheora? May be some drafts? May be frame dataflow throw encoder stages? PLEASE -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.xiph.org/pipermail/theora/attachments/20110318/c3e8e109/attachment.htm
2013 Oct 05
1
OPUS implementation with FPGA
Just to make sure, what's the goal here? Is the goal 1) to have a fast Opus implementation or are you 2) looking for an interesting FPGA implementation project? If 1), then an FPGA is most likely not necessary since Opus is not computationally expensive. If 2), then it depends on the desired size of the project and the desired quality. The simplest encoder possible is indeed simpler than the
2008 Sep 03
1
[LLVMdev] LLVM FPGA interface.
Hi LLVM community members. I downloaded LLVM-GCC4.2 Front-end source code and succefully installed alongwith LLVM-2.3 on linux x86_64. I think it's front-end has better optimizations. I am naive to LLVM environment, my focus is to generate LLVM inermediate code for FPGA. Are there any resources/links/papers/documents which discusses LLVM intermediate generation for FPGA needs. I am aware
2011 Aug 22
1
[LLVMdev] llvm-fpga microblaze target
folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.
2013 Oct 04
3
OPUS implementation with FPGA
Hi, We would like to use the OPUS codec @ 16 kHz sampling rate and max 32 kbps. What about implementing an OPUS coder and decoder in an FPGA? Has this been done? Would either coder or decoder more suitable for FPGA implementation? Best regards Fredrik Bonde -------------- next part -------------- An HTML attachment was scrubbed... URL:
2007 May 07
2
Theora running on FPGA
Great news! Theora is running on FPGA. After almost a year of a great effort we have Theora validated on FPGA. Now I will try to integrated the hardware with a video controller to see the video! I completely implemented the ExpandBlock, CopyRecon, LoopFilter and UpdateUMVBorder functions. The ReconRefFrames function was partially implemented and the part before will run on a software compiled
2008 Feb 01
6
Dynamic Change Parameters..
I am going to improve theora codec with dynamically changing way. In this case we want to change compression parameters like video_q, sharpness when a keyframe is generated. When i set video quality parameter using cpi-> pb.info.quality in CommpressKeyFrame in encoder_toplevel it will not change dynamically. Can you please help me to do this. Wich function should i cange to achieve my
2005 Apr 08
2
oggzinfo buglet
Conrad, Small buglet with the 0.9.1 liboggz release (go dude!) http://thaumas.net/~giles/xiph/elphel/clips/elphel_00017.ogg causes a float exception in oggzinfo when it tries to calculate the bitrate. It fails to measure the duration and tries to divide by zero. :) There may well be something wrong with the file, although oggz-validate doesn't complain. Also, the configure script
2011 Aug 21
0
[LLVMdev] Xilinx zynq-7000 (7030) as a Gallium3D LLVM FPGA target
Luke Kenneth Casson Leighton wrote: > On Sun, Aug 21, 2011 at 12:48 AM, Nick Lewycky<nicholas at mxc.ca> wrote: > >> The way in which Gallium3D targets LLVM, is that it waits until it receives >> the shader program from the application, then compiles that down to LLVM IR. >> That's too late to start synthesizing hardware (unless you're planning to >>
2011 Aug 21
4
[LLVMdev] Xilinx zynq-7000 (7030) as a Gallium3D LLVM FPGA target
On Sun, Aug 21, 2011 at 12:48 AM, Nick Lewycky <nicholas at mxc.ca> wrote: > The way in which Gallium3D targets LLVM, is that it waits until it receives > the shader program from the application, then compiles that down to LLVM IR. > That's too late to start synthesizing hardware (unless you're planning to > ship an FPGA as the graphics card, in which case reprogramming