similar to: [PATCH 0/5] renouveau: nv30/nv40 unification

NV10TCL defines the vertex buffer registers both as arrays and as individual named registers. This causes duplicate register definitions and the individual registers are not used either by the DDX or by the Mesa driver. Francisco Jerez said to remove them all. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> --- renouveau.xml | 49

First some data errors I get with both nv20 exa and nv20 dri/mesa. 1. RT_FORMAT LINEAR + X8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000105 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000105 LINEAR + A8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000108 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000108 The only value I found in renouveau dump

Hi, This is my work in documenting EVO. I did some RE to fill missing gaps. Best regards, Maxim Levitsky

--- rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml index 500cea9..e006dbe 100644 --- a/rnndb/memory/nvc0_pbfb.xml +++ b/rnndb/memory/nvc0_pbfb.xml @@ -49,23 +49,54 @@ Most bitfields are unknown. </doc> <bitfield high="7"

Hello, I've recently come across an error reported by the GPU and would like to know what it means and especially what causes it to be triggered. Any information would be very useful: I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is what we currently have in nouveau: <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched -->

Currently the nv30 and nv40 Gallium drivers are very similar, and contain about 5000 lines of essentially duplicate code. I prepared a patchset (which can be found at http://repo.or.cz/w/mesa/mesa-lb.git/shortlog/refs/heads/unification+fixes) which gradually unifies the drivers, one file per the commit. A new "nvfx" directory is created, and unified files are put there one by one.

Hi Robert, Thanks for the quick response! That goes in line with my observations which is that these things happen when using an ATOM/RED instruction. I've checked and rechecked that I'm generating ops with identical bits as what the proprietary driver does, however (and nvdisasm prints identical output). Could you advise what the proper way of indicating that the memory is

--- rnndb/display/nv3_pramdac.xml | 67 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/rnndb/display/nv3_pramdac.xml b/rnndb/display/nv3_pramdac.xml index 13b6a7b..e236921 100644 --- a/rnndb/display/nv3_pramdac.xml +++ b/rnndb/display/nv3_pramdac.xml @@ -79,12 +79,79 @@ <bitfield pos="28" name="VCLK_DB2"/> <bitfield

I'm especially interested in the original data that was used to derive the constant buffer arguments. I'm looking for the texture unit switch for tiling format, and i'm hoping the original data will easily reveal it. Maarten.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Perhaps there was a day when those were different, but that day is not today. src/gallium/drivers/nouveau/nv30/nv30_context.c | 1 - src/gallium/drivers/nouveau/nv30/nv30_context.h | 1 - src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c | 20 ++++++++++---------- src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c | 8 ++++---- 4

Hi, I have an UPS with only the marking D1000 on it and it came with Junda-Tech's UpsMate. Its USB id is 3344:0025, which is apparently a microprocessor. I've could get some of the HID interactions as described on the website, but there are some outstanding. Junda-Tech does not respond to any queries. Does anybody else have the same or a similar UPS with more information? What is the

--- generator/generator_gobject.ml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generator/generator_gobject.ml b/generator/generator_gobject.ml index e4c175b..48ddbf0 100644 --- a/generator/generator_gobject.ml +++ b/generator/generator_gobject.ml @@ -391,7 +391,7 @@ let generate_gobject_optargs_source name optargs flags () = pr "G_DEFINE_TYPE(%s, guestfs_%s,

Hi, As I'm looking to add some support to nouveau for features like atomic counters and images, I'm running into some confusion about what the first word of the shader header means. Here is the definition as we have it today: https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_shaders.xml VS/HS/DS/GS: <reg32 offset="0" name="0"> <bitfield

This patch series silences some unknown cap warnings and fixes up coding style (patch 1+4). The most important part of this series are the two patches in the middle. They rework the state_fb code, so that we are able to render to not 64 byte aligned targets, as this is the only real use-case for render temporaries this allows us to drop temp code completely and simplifies a lot

Hi, I'm having an issue with subregisters on my target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> =

- This avoids problematic "reloc'ed while mapped" messages and some associated corruption as well. Signed-off-by: Maarten Maathuis <madman2003 at gmail.com> --- src/gallium/drivers/nouveau/nouveau_screen.c | 21 +++++++++++++++++++++ src/gallium/drivers/nouveau/nouveau_screen.h | 3 +++ src/gallium/drivers/nouveau/nouveau_stateobj.h | 13 +++++++++++++

Hello, At the risk of looking like an idiot, I thought I would post because I can't make Koala's script work. My brother has an nVidia GEforce 8800, which nobody has dumped for, so I thought I would try. As I posted here: https://answers.launchpad.net/ubuntu/+question/29595 I am trying to submit a REnouveau dump from my brother's computer. I have installed the latest Ubuntu Hardy

Hello, I have two problems: 1) Identify my card 2) Error message at dumping 1) It seems to me that I have a special version of the GeForce4 420 Go 32M because my card is a GeForce4 440 Go 64M but both have the same PCI device id. Is this important for the development of the renouveau driver or is this already noted? Outputs: lspci [...] 01:00.0 VGA compatible controller: nVidia Corporation

Hello, I have a dual-GPU card GeForce 7950 GX2 (PCI ID 10de:0294). Unfortunately, I cannot make a dump using renouveau, because the program crashes. The backtrace looks like this: Program received signal SIGSEGV, Segmentation fault. 0x00000000004153af in read_fb_ramin (instanceMem=4, offset=2) at objects.c:4089 4089 return fb[((fb_size - (ramin_block*512*1024) + ramin_inst)/4) +

Hello, I have my work on the nv vpe video decoder in a functional state. In case you didn't know this decoder accelerates mpeg2 video at the idct/mc level. I have verified that it works on nv40 hardware. I believe it works on nv30 hardware (and maybe some earlier hardware), but I cannot verify since I have none. I will reply with patches against the kernel, drm, ddx and mesa for