Displaying 20 results from an estimated 10000 matches similar to: "Unable to use RegisterClass(&WndClass);"
2013 Jun 25
2
[LLVMdev] Adding a new ARM RegisterClass
I'm looking at an issue where we want a particular pseudo-instruction to
choose from a set of registers that is not included in the existing set of
RegisterClass definitions. More concretely, there is a RegisterClass in
ARMRegisterInfo.td defined as
def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
let
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
Hi, everyone.
I' have three set of registers - read-only regs, general purpose regs
(read and write), and write-only regs. How should I partition them
into different RegisterClasses so that I can easy define the
instruction?
All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.
def
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
All registers in my hardware are 4-element vector registers (128-bit).
Some are floating point registers, and the others are integer
registers.
I typedef two packed classes: [4 x float] and [4 x int], and add an
enum 'packed' to MVT::ValueType (ValuesTypes.h).
I declared all 'RegisterClass'es to be 'packed' (first argument of
RegisterClass):
def GeneralPurposeRC :
2018 Apr 12
0
How to specify the RegisterClass of an IMPLICIT_DEF?
On 4/12/2018 8:01 AM, Dominique Torette via llvm-dev wrote:
>
> But there is one small issue in the inference of RegisterClass of the
> implicitly defined register.
>
> As shown below, the %vreg6<def> is implicitly defined as FPUabRegisterClass.
>
> This register class accepts the v2f32 type, but for others addressing
> mode context this register should be
2005 Jul 25
2
[LLVMdev] How to partition registers into different RegisterClass?
Thanks, I think it can solve my problem.
But please allow me to explain the hardware in detail. Hope there is
more elegant way to solve it.
The hardware is a "stream processor". That is, It processes samples
one by one. Each sample is associated with several 128-bit
four-element vector registers, namely:
* input registers - the attributes of the sample, the values of the
registers
2014 Jan 19
2
[LLVMdev] Why make the register list a dag for RegisterClass in target descriptor file?
The blow snippet in target.td shows the regList in RegisterClass is typed
as dag. Why not make it a simple list, such as list<Register>?
class RegisterClass<string namespace,
list<ValueType> regTypes, int alignment, dag regList>
Thanks,
-Thomson
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2019 Jul 18
2
Question about TableGen RegisterClass definition
Hi All,
I have a question about TableGen RegisterClass definition.
I need to map different size of MVTs into a register class as below.
def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>
When I look at TableGen and CodeGen, it looks the types are used as following:
1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction
2006 May 13
2
[LLVMdev] TableGen: RegisterClass question
Hi,
I'm porting some existing code of mine to CVS HEAD, and don't understand
something about new RegisterClass TableGen definition:
class RegisterClass<string namespace, list<ValueType> regTypes,........
{
.....
string Namespace = namespace;
What is this "namespace" thing? It looks like it should contain the name of
backend, right?
// RegType
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
Hi,
I'm implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture.
def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)),
(INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
(i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote:
> I' have three set of registers - read-only regs, general purpose regs
> (read and write), and write-only regs. How should I partition them
> into different RegisterClasses so that I can easy define the
> instruction?
[snip]
> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
>
2005 Jul 25
1
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/24, Chris Lattner <sabre at nondot.org>:
> Ah, ok. In that case, you want to put all of the registers in one register
> file, and not make the constant register allocatable (e.g. see
> X86RegisterInfo.td, and note how the register classes include EBP and ESP,
> but do not register allocate them (through the definition of
> allocation_order_end()).
>
> -Chris
2013 May 23
3
[LLVMdev] Definition of RegisterClass for load instruction in Thumb2
Hi,
I have a question about the definitions of t2LDRSB and t2LDRSB_PRE in ARMInstrThumb2.td :
I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced?
2013 May 23
0
[LLVMdev] Definition of RegisterClass for load instruction in Thumb2
Hi Junbum,
> I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced?
They're not allocated during CodeGen because of the Reserved.set(…) calls in
2012 Oct 04
1
[LLVMdev] RegisterClass constraints in TableGen
Hi,
I've come across a problem while working on an LLVM backend for a new
target architecture.
This architecture has two single-ported register files. Each instruction
can only read one operand from each register file, but can write to either.
I tried implementing it naïvely in TableGen with two definitions per
instruction, so I had:
def AllRegs : RegisterClass< ... (add interleave
2001 Aug 10
3
specuak chars
Hi,
can anyone tell how to enter special characters like vowels with accents or
the spanish "?"?
For Linux apps I can enter them by typing a special key sequence, e.g.:
? : [CTRL] [?] [a]
When windows booted directly this also works. Alternatively it is possible
to enter the ASCII-number by pressing [Alt].
Well, when I start a windows application with wine none ot the
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
On Fri, 22 Jul 2005, Tzu-Chien Chiu wrote:
> All registers in my hardware are 4-element vector registers (128-bit).
> Some are floating point registers, and the others are integer
> registers.
>
> I typedef two packed classes: [4 x float] and [4 x int], and add an
> enum 'packed' to MVT::ValueType (ValuesTypes.h).
>
> I declared all 'RegisterClass'es to be
2005 Jul 23
0
[LLVMdev] How to partition registers into different RegisterClass?
On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote:
> 2005/7/23, Chris Lattner <sabre at nondot.org>:
>> What does a 'read only' register mean? Is it a constant (e.g. returns
>> 1.0)? Otherwise, how can it be a useful value?
>
> Yes, it's a constant register.
>
> Because the instruction cannot contain an immediate value, a constant
> value may be stored in
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2005 Jul 26
0
[LLVMdev] How to partition registers into different RegisterClass?
On Mon, 25 Jul 2005, Tzu-Chien Chiu wrote:
> But please allow me to explain the hardware in detail. Hope there is
> more elegant way to solve it.
Sounds good!
> The hardware is a "stream processor". That is, It processes samples
> one by one. Each sample is associated with several 128-bit
> four-element vector registers, namely:
>
> * input registers - the
2007 Feb 12
2
[LLVMdev] bitconvert for multi-typed RegisterClasses
Hi All,
I'm working on a back end for an architecture that makes use of multi-
typed register classes.
def MR: RegisterClass<"namespace", [type1, type2, ... ], ... >
When running some preliminary tests I found that the instruction
selector refused to select certain ops (specifically stores) for some
instructions when the operand type wasn't the first type for the