similar to: Reading a file line by line - separating lines VS separating columns

Hello, I am trying to complete a PCA on a set of standardized ring widths from 8 different sites (T10, T9, T8, T7, T6, T5, T3, and T2). The following is a small portion of my data: T10 T9 T8 T7 T6 T5 T3 T2 1.33738 0.92669 0.91146 0.98922 0.9308 0.88201 0.92287 0.91775 0.82181 1.05319 0.92908 0.97971 0.95165 0.98029 1.14048 0.77803 0.88294 0.96413 0.90893 0.87957 0.9961 0.74926 0.71394 0.70877

dear list: I need help to achieve a simpler code to complete a task I'm performing. here is an example: dat<-expand.grid(a=seq(1,5),b=seq(1000,1005)) I want to add a new column dat$c in that: t1<-ifelse(dat$a==1&dat$b==1001,1001,0) t2<-ifelse(dat$a==2&dat$b==1002,1001,0) t3<-ifelse(dat$a==3&dat$b==1003,1001,0) t4<-ifelse(dat$a==1&dat$b==1002,1002,0)

Dear R-users, actually i try to parse some state protocols for my work. i an easy stetting the code below works fine, if states are reached only once. in harder settings it could be possible that one state gets visited more times. in this case for me its interesting to see how much waiting time lies between to states on the whole. by the way i didn't use R as a parsing tool so far, so

Dear all, Please suggest me how can I do it. I have a matrix which look like following: x1 x2 x3 t1 .01 0.3 0 t2 0 0.1 0.01 t3 0 .01 .01 t4 0 0 t5 5 0 0 t6 0 0 0 t7 0 0 0 t8 0 0 0 t9 0.6 0 0 t10 0 0 0.66 t11 0 0.6 0.11 t12 0 0.4 0 I want to sort decreasing order in each column based on rows. and then to display only those rows which has a value. The expected out put matrix will

Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"

Hi to all the people again, I was writting a simply function in R, and wish to collect the results in a excel file. The work goes as follows, Ciervos<-function(K1, K0, A, R,M,Pi,Hembras) {B<-(K1-K0)/A T1<-(R*Pi*Hembras-M*Pi+B)/(Pi-M*Pi+R*Pi*Hembras) P1<-Pi-B R1<-P1*Hembras*R M1<-P1*M T2<-(R1-M1+B)/(P1-M1+R1) P2<-P1-B R2<-P2*Hembras*R M2<-P2*M

Is there any way to get it to delay this optimization where it goes from this: Initial selection DAG: BB#0 'bclr64:entry' SelectionDAG has 14 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6

We've recently moved our project from LLVM 3.6 to LLVM 3.9. I noticed one of our code generation tests is breaking in 3.9. The test is: ; RUN: llc < %s -march=xstg | FileCheck %s define i64 @bclr64(i64 %a, i64 %b) nounwind readnone { entry: ; CHECK: bclr r1, r0, r1, 64 %sub = sub i64 %b, 1 %shl = shl i64 1, %sub %xor = xor i64 %shl, -1 %and = and i64 %a, %xor ret i64

Setting the ISD::ROTL to Expand doesn't work? (via SetOperation) You could also do a Custom hook if that's what you're looking for. On Thu, Nov 3, 2016 at 5:12 PM, Phil Tomson <phil.a.tomson at gmail.com> wrote: > ... or perhaps to rephrase: > > In 3.9 it seems to be doing a smaller combine much sooner, whereas in 3.6 > it deferred that till later in the

I have a rather basic set of data. It is simply a variable that can be 0, 1 or 2 and its value over a series of time t0 - t9 like so: y: 1 1 2 0 1 2 2 1 2 1 x: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 I need to predict what the value of y will be at t10 through t13. As you can see its rather basic. I am rather new to solving these types of problems so I am looking for some good straight forward things

One option may be to prevent the formation of ROTL, if possible, and then generating rol by hand. Marking it as "expand" would likely stop the DAG combiner from creating it. Then you could "preprocess" the selection DAG before the instruction selection and do the pattern matching yourself. -Krzysztof On 11/3/2016 4:24 PM, Phil Tomson via llvm-dev wrote: > I could try

Thank you. i understood how avx512 vector instructions are written in x86instravx512. i need to define my vector instructions so i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))],

also i further run the following command; llc -debug filer-knl_o3.ll and its output is attached here. by looking at the output can we say that legalization runs fine and the error is due to instruction selection/ pattern matching which is not yet implemented? so do i need to worry and try to correct it at this stage or should i move forward to implement instruction selection/ pattern matching?

Thank you; i have changed as follows.is it fine now? def VADD_256B : I<0xFE, MRMDestReg, (outs VR2048:$dst), (ins VR2048:$src1, VR2048:$src2), "VADD_256B\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (add VR2048:$src1, VR2048:$src2))]]>; Also here i have changed class RI to I. Does it make any difference? On Sat, Jul 8, 2017 at 9:38 AM, Craig Topper

On Tue, Dec 13, 2016 at 06:22:41PM -0700, The Doctor wrote: > On Wed, Dec 14, 2016 at 12:12:21PM +1100, Damien Miller wrote: > > On Tue, 13 Dec 2016, The Doctor wrote: > > > > > Got you. Will run make tests. So far running on > > > FreeBSD 11.0 using openssl 1.0.2 current > > > > Thanks! > > Point of concern > > run test sftp-perm.sh

Thank You. I have seen the opcode is 8 bits and all the combinations are already used in llvm x86. Now what to do? On Sat, Jul 8, 2017 at 10:57 AM, Craig Topper <craig.topper at gmail.com> wrote: > Yes its an opcode conflict. You'll have to look through Intel documents > and find an unused opcode. I've only added instructions based on a real > spec so I don't know

On 05/03/2024 01:24, Damien Miller wrote: > > Hi, > > OpenSSH 9.7p1 is almost ready for release, so we would appreciate testing > on as many platforms and systems as possible. This is a bugfix release. > Running the testsuite on Solaris 9 I see this: set -xe ; if /export/home/tgc/buildpkg/openssh/src/openssh-git/ssh -Q key | grep -q ^ssh-rsa ; then \

> The underlying liveness datastructure is a list of ranges where each vreg is alive > (ranges in terms of instructions numbered). I remember a couple of later linear scan > papers describing the same thing (Traub et.al. being the first if I remember correctly). > That should be as accurate as you can get in terms of liveness information. It depends on the details. For example, given

Hello, i am experimenting with the increase in register/ vector width to 64 elements of 32 bits instead of 16 in x86 backend. for eg. i have a loop with 65 iterations; if my IR generates v64i32 and 1 scalar, still the backend breaks the v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 elements in loop then it should break it into 2 v64i32 instructions. in order to do this i

Hello, I am new to using R and I am having problems get boot() to work properly. Here is what I am trying to do: I have statistic called "cs". cs takes a data matrix (154 x 5) and calculates 12 different scores for me. cs outputs the data as a vector (12 x 1). cs doesn't really use weights, per se, however I have included this as one of the 2 arguments cs can take. I try