search for: zero_regs

Displaying 8 results from an estimated 8 matches for "zero_regs".

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2015 Sep 22
2
zero_reg
Hi all, what is exactly "zero_reg"? from ARMInstFromats.td: *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> {...}* I thought zero_reg can be replace by a random name like (alu_stat_reg for alu state register) but when I compiled it, I figure out that zero_reg is a predefined variable. Can someone please give me more information about
2015 Dec 14
2
Tablegen definition question
Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand";
2015 Dec 14
2
Tablegen definition question
Hi All, In ARMInstFormats.td predicate is defined this way: *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),* *(ops (i32 14), (i32 zero_reg))> {...}* I use the same definition in my code. But I have another version of predicate which is exactly the same but it is a condition code plus a quantifier! (e.g. Xpred = (pred + i32imm)). I was wondering how we can define a sub sub
2015 Dec 14
2
Tablegen definition question
Hello James, that was also what I've planned to do but just wasn't sure. Thanks for that. On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk> wrote: > Hi, > > You can't nest operands like that - it must be a flattened list. So: > > def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm), > (ops (i32 14), (i32
2011 Sep 07
1
[LLVMdev] ARM CPSR liveness
All, ARM LLVM afficianados: I'm trying to understand how LiveVariables computes liveness for CPSR. In particular, I would like to tell whether a particular instruction is a use/kill/def for doing some within block liveness checking I need. Thanks in advance, David -------------- next part -------------- An HTML attachment was scrubbed... URL:
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
Hi Daniel, Thanks for replying; I was hoping to get in touch with you on this issue. I had a look at how SelectionIDAG does it when generating the matcher table, and it does consider the implicit defs as additional output. Here is the match table generated for the pattern: /* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND), /* 3*/ OPC_MoveChild0, /* 4*/ OPC_CheckOpcode,
2015 Oct 28
0
Isohybrid wiki page and UEFI
...turn __bad_SEG(const volatile void *p) { dprintf("SEG() passed an invalid pointer: %p\n", p); kaboom(); } #endif So IIUC it should include that function if CORE_DEBUG is set to 1 no ? However: # nm ./bios/core/kaboom.o U call16 U kaboom 00000000 T _kaboom U zero_regs So I commented the #if and #endif and now it's compiling further. I'm not sure why it fails but that's a workaround for me now. Bruno. -- Open Source Profession, Linux Community Lead WW http://opensource.hp.com HP EMEA EG Open Source Technology Strategist http://hpintelco.n...
2015 Oct 28
2
Isohybrid wiki page and UEFI
On Tue, Oct 27, 2015 at 10:15 PM, Bruno Cornec via Syslinux <syslinux at zytor.com> wrote: > Bruno Cornec via Syslinux said on Wed, Oct 28, 2015 at 01:45:22AM +0100: >> >> Is there a way to increase the debug level of syslinux.efi in order to >> check what it tries to do and diagnose more precisely what happens ? > > > Ok, I tried to modify mk/devel.mk to put: