Displaying 8 results from an estimated 8 matches for "zero_reg".
2015 Sep 22
2
zero_reg
Hi all,
what is exactly "zero_reg"?
from ARMInstFromats.td:
*def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14),
(i32 zero_reg))> {...}*
I thought zero_reg can be replace by a random name like (alu_stat_reg for
alu state register) but when I compiled it, I figure out that zero_reg is a
predefined...
2015 Dec 14
2
Tablegen definition question
...DecoderMethod is for. Similarly ParserMatchClass for the
asm parser and PrintMethod for the asm printer:
def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
let ParserMatchClass = CondCodeOperand;
let DecoderMethod = "DecodePredicateOperand";
}
James
On Mon, 14 Dec 2015 at 13:44 Sky Flyer <skylake007 at googlemail.com> wrote:
> But one question!
>
> imagine I...
2015 Dec 14
2
Tablegen definition question
Hi All,
In ARMInstFormats.td predicate is defined this way:
*def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),*
*(ops (i32 14), (i32 zero_reg))> {...}*
I use the same definition in my code. But I have another version of
predicate which is exactly the same but it is a condition code plus a
quantifier! (e.g. Xpred = (pred + i32imm)).
I was wondering how we can define a sub sub operand, something like this:
def *Xpred* : PredicateOpe...
2015 Dec 14
2
Tablegen definition question
...that.
On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk>
wrote:
> Hi,
>
> You can't nest operands like that - it must be a flattened list. So:
>
> def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm),
> (ops (i32 14), (i32 zero_reg))> {...}
>
> On Mon, 14 Dec 2015 at 10:21 Sky Flyer via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hi All,
>>
>> In ARMInstFormats.td predicate is defined this way:
>>
>>
>>
>> *def pred : PredicateOperand<OtherVT, (ops i32...
2011 Sep 07
1
[LLVMdev] ARM CPSR liveness
All,
ARM LLVM afficianados: I'm trying to understand how LiveVariables computes
liveness for CPSR. In particular,
I would like to tell whether a particular instruction is a use/kill/def for
doing some within block liveness checking I need.
Thanks in advance,
David
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2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...e::INSERT_SUBREG), 0,
MVT::i32, 3/*#Ops*/, 3, 0, 4, // Results = #5
/* 54*/ OPC_EmitNode1, TARGET_VAL(OurTarget::clearLo32_pseudo), 0,
MVT::i32, 1/*#Ops*/, 5, // Results = #6
/* 61*/ OPC_EmitInteger, MVT::i16, 0,
/* 64*/ OPC_EmitRegister, MVT::i16, 0 /*zero_reg*/,
/* 67*/ OPC_EmitInteger, MVT::i16, 0,
/* 70*/ OPC_EmitNode2, TARGET_VAL(OurTarget::shfts_a32_imm7), 0,
MVT::i32, MVT::i16, 5/*#Ops*/, 6, 1, 7, 8, 9, // Results =
#10 #11
/* 82*/ OPC_EmitInteger, MVT::i32, OurTarget::acc,
/* 85*/ OPC_EmitNode1, TARGET_VAL(TargetO...
2015 Oct 28
0
Isohybrid wiki page and UEFI
...turn __bad_SEG(const volatile void *p)
{
dprintf("SEG() passed an invalid pointer: %p\n", p);
kaboom();
}
#endif
So IIUC it should include that function if CORE_DEBUG is set to 1 no ?
However:
# nm ./bios/core/kaboom.o
U call16
U kaboom
00000000 T _kaboom
U zero_regs
So I commented the #if and #endif and now it's compiling further. I'm
not sure why it fails but that's a workaround for me now.
Bruno.
--
Open Source Profession, Linux Community Lead WW http://opensource.hp.com
HP EMEA EG Open Source Technology Strategist http://hpintelco....
2015 Oct 28
2
Isohybrid wiki page and UEFI
On Tue, Oct 27, 2015 at 10:15 PM, Bruno Cornec via Syslinux
<syslinux at zytor.com> wrote:
> Bruno Cornec via Syslinux said on Wed, Oct 28, 2015 at 01:45:22AM +0100:
>>
>> Is there a way to increase the debug level of syslinux.efi in order to
>> check what it tries to do and diagnose more precisely what happens ?
>
>
> Ok, I tried to modify mk/devel.mk to put: