Displaying 4 results from an estimated 4 matches for "z80instr".
Did you mean:
x86instr
2012 Apr 25
2
[LLVMdev] LLVM Backend for Z80. ADD -> replaced -> OR
...th 1" will work, but for second assigned :OR with 2" will not work.
I suspect that llc is assuming that HL will contain 8 (that's the start) and
or-ing 8 with 1 or with 2 is ok.
But my HL has also added SP to it.
This is how my ISD::FrameIndex instruction look like:
def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src),
"ld $dst, $disp\n\tadd $dst,$src",
[(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>;
So it say that HL16:$dst wich is only HL register, will be changed.
I also tried to change it to
<(outs HL16:$dst), (ins i16imm:$disp, SP...
2012 Apr 25
0
[LLVMdev] LLVM Backend for Z80. ADD -> replaced -> OR
...assigned :OR with 2" will not
> work.
>
> I suspect that llc is assuming that HL will contain 8 (that's the start)
> and or-ing 8 with 1 or with 2 is ok.
> But my HL has also added SP to it.
> This is how my ISD::FrameIndex instruction look like:
>
> def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src),
> "ld $dst, $disp\n\tadd $dst,$src",
> [(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>;
>
> So it say that HL16:$dst wich is only HL register, will be changed.
> I also tried to change it to
> <(outs HL16:$...
2012 Apr 25
1
[LLVMdev] LLVM Backend for Z80. ADD -> replaced -> OR
...ot
>> work.
>>
>> I suspect that llc is assuming that HL will contain 8 (that's the start)
>> and or-ing 8 with 1 or with 2 is ok.
>> But my HL has also added SP to it.
>> This is how my ISD::FrameIndex instruction look like:
>>
>> def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src),
>> "ld $dst, $disp\n\tadd $dst,$src",
>> [(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>;
>>
>> So it say that HL16:$dst wich is only HL register, will be changed.
>> I also tried to change it to
&...
2012 Apr 18
0
[LLVMdev] [cfe-dev] LLVM Backend for Z80
...;viewGraph().
Maybe that gives you an idea where the problem could be.
Cheers,
Jonas
Am 16.04.2012 um 12:51 schrieb Peter Hanzel:
> Hello.
>
> I am playing with LLVM and trying to create Zilog Z80 Backend.
> I have succesfully created basic infrastructure and now trying to extend Z80InstrInfo.td to handle more and more C code.
> I have done some work with FrameIndex and now I am stuck with assert.
>
> llc: SelectionDAG.cpp:645: bool llvm::SelectionDAG::RemoveNodeFromCSEMaps(llvm::SDNode*): Assertion `N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMa...