Displaying 7 results from an estimated 7 matches for "x86instr".
2010 Mar 25
1
[LLVMdev] TSFlagsFields and TSFlagsShifts obsolete?
...work just fine:
class Instruction {
bits<32> TSFlags;
}
class Domain<bits<2> val> {
bits<2> Value = val;
}
def GenericDomain : Domain<0>;
def SSEPackedInt : Domain<1>;
def SSEPackedSingle : Domain<2>;
def SSEPackedDouble : Domain<3>;
class X86Instr<bits<8> opcod> : Instruction {
Domain ExeDomain = GenericDomain;
let TSFlags{0-7} = opcod;
let TSFlags{22-23} = ExeDomain.Value;
}
class PIInstr<bits<8> opcod> : X86Instr<opcod> {
let ExeDomain = SSEPackedInt;
}
def i1 : X86Instr<0x12>;
def i2 : PIInstr...
2017 Dec 11
2
New x86 instruction with opcode 0x0F 0x7A
Hi all,
I'm trying to simulate an extended x86 architecture on gem5 with several
new instructions. My hardware setup is done and now I'd like llvm to accept
the existence of the new instruction passed in inline assembly and output
the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and
I would like the instruction to have the same operands and return values
as CVTPS2PI
2018 Mar 18
0
Generating a custom opcode from an LLVM intrinsic
Here's a couple examples for mapping an intrinsic to an X86 instruction
from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
find others.
let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
I...
2018 Mar 19
4
Generating a custom opcode from an LLVM intrinsic
...re, though I guess I should have looked harder -- the hex
should have given me a clue, perhaps!
For the sake of my own edification (and not taking up too much of your
time) I will try to generate it myself. I've found the definition of the
"I" class at line 358 of llvm/lib/Target/X86/X86InstrFormats.td, which
helps a lot.
Let's assume I want to produce opcode 0x16 (which I'm using because it
doesn't seem to be implemented in gem5 otherwise, and would simply produce
a warning). Then my guess is that I should use something like:
def CACHEADD : I<0x16, FORMAT, (outs), (ins)...
2018 Mar 18
2
Generating a custom opcode from an LLVM intrinsic
Hello all. LLVM newbie here. If anything seems glaringly wrong with my use
of LLVM, that's probably why.
Here's what I'm trying to do. I have modified the gem5 simulator to accept
a "new" x86 instruction. I've done this by just reserving the opcode in
gem5's ISA specification, just as all other instructions are specified.
I'm trying to get an LLVM backend to
2018 Mar 19
0
Generating a custom opcode from an LLVM intrinsic
...uld have looked harder -- the hex
> should have given me a clue, perhaps!
>
> For the sake of my own edification (and not taking up too much of your
> time) I will try to generate it myself. I've found the definition of the
> "I" class at line 358 of llvm/lib/Target/X86/X86InstrFormats.td, which
> helps a lot.
>
> Let's assume I want to produce opcode 0x16 (which I'm using because it
> doesn't seem to be implemented in gem5 otherwise, and would simply produce
> a warning). Then my guess is that I should use something like:
> def CACHEADD : I&l...
2018 Mar 20
1
Generating a custom opcode from an LLVM intrinsic
...hen I wrote this email. I'm
moving on to a more complex goal now, but the original question was
answered completely, in my opinion. This was the key line:
def CACHEOP : I<0x06, RawFrm, (outs), (ins), "cache_op", [(int_cache_op)]>;
I added this definition to llvm/lib/Target/X86/X86InstrInfo.td. I also had
to comment out an instruction (PUSHES) which overlapped the 0x06 opcode.
This was OK in my case (as far as I know) because PUSHES isn't implemented
in gem5.
Thanks again!
Gus
On Sun, Mar 18, 2018 at 11:30 PM, Craig Topper <craig.topper at gmail.com>
wrote:
> ASM...