search for: z80

Inspired by Jason Turner's talk at CppCon 2016: Jason Turner “Rich Code for Tiny Computers: A Simple Commodore 64 Game in C++17” I got interested in writing a Zilog Z80 backend for LLVM. Jason actually did no such thing, but instead wrote a x86-to-6502 translator (reassembler he calls it) https://github.com/lefticus/x86-to-6502 So I'm now trying to bootstrap this project. Goal: - be able to use C++17 (or whatever is supported of that in clang-master) on my Z...

Hi All. I'm writing storeRegToStackSlot and loadFromStackSlot function for my Target. This Target can store/load one byte (not all word) from FrameIndex. If I need to store 16 bit register I will must to split it to two instruction like this: BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(0) .addReg(SrcReg, 0, Z80::subreg_lo); BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(1) .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); After this store I catch assertion failed: "Instruction not foun...

I'm working on a Z80 backend and am trying to efficiently lower SEXT, specifically 8 to 16 bit, in LowerOperation() according to the following rules: The Z80 has 8 bit registers and 16 bit registers, which are aliased versions of two 8 bit registers. 8 bit registers are named A, H, L, D, E and some more. 16 bit re...

Hi, I'm trying to revive jacobly0's Z80 back-end (from https://github.com/jacobly0/llvm-z80) and build it with a current version of LLVM. Apart from some interface changes, I'm stuck at building the tables. Specifically, the generation of the DAG instruction selector causes an assertion in the table generator: Assertion fa...

...> > I'm writing storeRegToStackSlot and loadFromStackSlot function for my > Target. This Target can store/load one byte (not all word) from FrameIndex. > If I need to store 16 bit register I will must to split it to two > instruction like this: > > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(0) > .addReg(SrcReg, 0, Z80::subreg_lo); > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(1) > .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); > > After this store I catch assertion...

...ses/3.0/docs/CodeGenerator.html#selectiondag_process) This takes some minimal effort to setup but is incredibly useful: Run llc with all -view… options on. This will get you a first idea on where the problem occurs. Then if you find the causing SelectionDAG pass, let's say your Select method in Z80IselDAGToDAG, then you can set a breakpoint there and watch the state of the selection DAG on each iteration via CurDAG->viewGraph(). Maybe that gives you an idea where the problem could be. Cheers, Jonas Am 16.04.2012 um 12:51 schrieb Peter Hanzel: > Hello. > > I am playing with...

Hello. I am playing with LLVM and trying to make Z80 (Zilog Z80) backend. The source code is attached. I have succesfully made some simple test. But now I have problem with ADD instruction. The source C code is: typedef struct { unsigned char id1; unsigned char id2; unsigned char id3; } testS; void simple() { testS test; test.id1 = 0x40; t...

Hi Peter, I think the problem is that you did not explicitly define stack alignment in Z80TargetMachine.cpp DataLayout("e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8") Try to add S16 to the string if your stack is 2-byte aligned. Refer to http://llvm.org/docs/LangRef.html#datalayout . If it does not work, try to specify the layout in the input module using target layout directive. D...

Hello. I have played with DataLayout and found a solution with is uknown to me. I added S16 and also s0:16:16, but it had not worked. Then I found that in Z80FrameLowering.h I am calling TargetFrameLowering with stack aligment set to 8. So I changed it to 2 bytes. But this also didn't help. Then I changed llc to show TargetDataLayout and found that a option is set to a0:0:64. So I changed my Z80DataLayout to a0:0:16. And voila, it started to work a...

I want to make Z80 codegen backend to the LLVM. CLang+LLVM looks perfect, while quick playing around. Some questions available: 1) Does LLVM support to generate "mixed" code ? For example: in microcontrollers world the subroutine call with const arguments may be decorated like this: call subroutine defw w...

I'm working on defining the instructions and implementing the lowering code for a Z80 backend. For now, the backend supports only the native CPU-supported datatypes, which are 8 and 16 bits wide (i.e. no 32 bit long, float, ... yet). So far, a lot of the simple stuff like immediate loads and return values is very straightforward, but now I got stuck with ISD::TRUNCATE, as in:...

...s the way how the instruction info table will be set-up, I appreciate your suggestions very much! Now that you mentioned using a the pseudo instruction for the possible 16 bit LD command combinations: Regarding the heavily overlapped register structure and the asymmetric instruction set of the Z80, would you recommend to try mapping more instructions in the form of generic pseudos that expand to multiple instructions during legalisation (leading to more custom lowering code), or try to map as many instructions and variations according to the allowed / limited operators as possible in a 1...

Hello. I write backend for Z80 cpu and I have some trouble with lowering load/store nodes to different machine opcodes. Some target instructions work with specified registers (not all registers in RegisterClass). Often it's one or two registers. I don't understand how use ComplexPattern in this case. But if I don'...

...;m writing storeRegToStackSlot and loadFromStackSlot function for > my Target. This Target can store/load one byte (not all word) from > FrameIndex. If I need to store 16 bit register I will must to > split it to two instruction like this: > > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).addImm(0) > .addReg(SrcReg, 0, Z80::subreg_lo); > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).addImm(1) > .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); > > After this stor...

>It should be possible to get llvm to produce very good code for the Z80... Yes, I was thinking that too. These techniques didn't exist back then, so I'm really looking forward to the point where the first regular C sources can be compiled and see the magic happening in action live :) ------------------------------------------------------------------------...

Thanks Bruce, and elaborately as ever. Again, I'm surprised about your very thorough Z80 knowledge when you said you only did little on the ZX81 in the eighties :D OK, understood. I was first thinking about doing something like this for small frames: 1. push bc # 1 byte; 11 cycles - part of call frame-cleanup: save scratch register +-----begin call-related 2. ld <rr>...

For a Z80 backend, "eliminateCallFramePseudoInstr()" shall adjust the stack pointer in three possible ways, e.g. after a function call, depending on the amount (= adjustment size) *and some other rules*: 1. via one or more target "pop <reg>" instructions (SP increments +2 per in...

This is a question about optimizing the code generation in a (new) Z80 backend: The CPU has a couple of 8 bit physical registers, e.g. H, L, D and E, which are overlaid in 16 bit register pairs named HL and DE. It has also a native instruction to load a 16 bit immediate value into a 16 bit register pair (HL or DE), e.g.: LD HL,<imm16> Now when having...

...u have an insane number of rules... >> It's not like it costs anything extra.... :) > Well...that's the attitude that got us operating systems that need a > gigabyte of memory just to boot, and processors clocked at 3GHz that > give me the same useful performance as my 4MHz Z80 twenty years ago. > ;) Nothing is free. Your argument is bogus - see above... again, a basic, properly configured firewall has negligible impact on pretty much any systems resources, even ancient ones... So, yeah, enabling a firewall on a mail server is essentially free, whether talking impact...