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...s architecture has two single-ported register files. Each instruction can only read one operand from each register file, but can write to either. I tried implementing it naïvely in TableGen with two definitions per instruction, so I had: def AllRegs : RegisterClass< ... (add interleave (XRegs, YRegs))>; and in the InstrInfo.td: def Instr_xy: Instruction(outs AllRegs:$dst), (ins XRegs:$src1, YRegs:$src2), "...", [(set AllRegs:$dst, (OpNode XRegs:$src1, YRegs:$src2))] def Instr_yx: Instruction(outs AllRegs:$dst), (ins YRegs:$src1, XRegs:$src2), "...", [(set AllRegs:$ds...