Displaying 2 results from an estimated 2 matches for "xyzinstrinfo".
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x86instrinfo
2019 Jan 22
2
Different SelectionDAGs for same CPU
Hi,
I used 2 different compilers to compile the same IR for the same custom target.
The LLVM IR code is
define i32 @_Z9test_mathv() #0 {
%a = alloca i32, align 4
%1 = load i32, i32* %a, align 4
ret i32 %1
}
Before instruction selection, the Selection DAGs are the same:
Optimized legalized selection DAG: %bb.0 '_Z9test_mathv:'
SelectionDAG has 7 nodes:
t0: ch = EntryToken
t4:
2019 Jan 26
2
Different SelectionDAGs for same CPU
...d explain this difference in behavior?
The second compiler looks like someone has added extra code to fold a
stack address calculation into the load operation that accesses the
variable.
> Where in the code should I look into?
It could be implemented in a couple of places. Most likely is that
XYZInstrInfo.td (or some related TableGen file) defines a
ComplexPattern that is used by the LDWI instruction definition. That
ComplexPattern tells pattern matching to call a specific function in
XYZISelDAGToDAG.cpp when deciding what to use for the LDWI operands.
That C++ function is probably what looks for an...