search for: x86instrinfo

...oc Now I may look into config/i386/i386.md, and look for mentioned *pushdi2_rex64, movdi_1_rex64, floatdidf2_sse_interunit and other patterns and study how they work. How to make the same annotation for clang output assembler code? test: .Leh_func_begin1: pushq %rbp # ??? what insn in X86InstrInfo.td? .Llabel1: movq %rsp, %rbp # ??? what insn in X86InstrInfo.td? .Llabel2: movq %rdi, -16(%rbp) # ??? what insn in X86InstrInfo.td? movq -16(%rbp), %rax # ??? what insn in X86InstrInfo.td? cvtsi2sdq %rax, %xmm0 # ??? what insn in X86InstrInfo.td? movsd %xmm0, -8(%rbp) # ??? what...

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, I would like to query the X86InstrInfo tables to determine if a given opcode is a load or store from stack. I see functions isFrameLoadOpcode and isFrameStoreOpcode in lib/Target/X86/X86InstrInfo.cpp that would provide the functionality I am looking for. However, these functions are static. What is the recommended way to perform such...

...6.md, and look for mentioned > *pushdi2_rex64, movdi_1_rex64, floatdidf2_sse_interunit and other > patterns and study how they work. > > How to make the same annotation for clang output assembler code? > > test: > .Leh_func_begin1: > pushq %rbp # ??? what insn in X86InstrInfo.td? > .Llabel1: > movq %rsp, %rbp # ??? what insn in X86InstrInfo.td? > .Llabel2: > movq %rdi, -16(%rbp) # ??? what insn in X86InstrInfo.td? > movq -16(%rbp), %rax # ??? what insn in X86InstrInfo.td? > cvtsi2sdq %rax, %xmm0 # ??? what insn in X86InstrInfo.td? > movs...

Hi, This patch fixes outs/ins of MOV16mr instruction of X86. Thanks. diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index e9a0431..f5b2064 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), "mov{b}...

...il.com> > Cc: Chris Lattner <sabre at nondot.org> > Signed-off-by: Ramkumar Ramachandra <artagnon at gmail.com> > --- > I've probably done something stupid; seems to build correctly, but > that's all I know. Also, tests are pending. > > lib/Target/X86/X86InstrInfo.td | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td > index f33ae2a..4950674 100644 > --- a/lib/Target/X86/X86InstrInfo.td > +++ b/lib/Target/X86/X86InstrInfo.td > @@ -1971,6 +1971,10 @@ def : InstAlias...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And yes, it's a good > idea, there are other passes which can make use of them, e.g. branch > shortening. > > Thanks, > > Evan > > >> Thanks, >&gt...

...re's a new patch that adds the infrastructure and the > implementation for X86, ARM and PPC of GetInstSize and > GetFunctionSize. Both functions are virtual functions defined in > TargetInstrInfo.h. > > For X86, I moved some commodity functions from X86CodeEmitter to > X86InstrInfo. > > What do you think? > > Nicolas > > > Evan Cheng wrote: >> >> I think both of these belong to TargetInstrInfo. And yes, it's a >> good idea, there are other passes which can make use of them, e.g. >> branch shortening. >> >> Tha...

...gt;> *pushdi2_rex64, movdi_1_rex64, floatdidf2_sse_interunit and other >> patterns and study how they work. >> >> How to make the same annotation for clang output assembler code? >> >> test: >> .Leh_func_begin1: >>  pushq %rbp          # ??? what insn in X86InstrInfo.td? >> .Llabel1: >>  movq  %rsp, %rbp  # ??? what insn in X86InstrInfo.td? >> .Llabel2: >>  movq  %rdi, -16(%rbp)  # ??? what insn in X86InstrInfo.td? >>  movq  -16(%rbp), %rax  # ??? what insn in X86InstrInfo.td? >>  cvtsi2sdq %rax, %xmm0  # ??? what insn in X86...

I'm noticing the X86InstrInfo::GetInstSizeInBytes() function returning incorrect sizes for some instructions. I looked through the llvm-dev archives and noticed that a patch was submitted once in April 2009 for instruction length calculation on amd-64. I'm using Intel Core 2 Duo (64 bit) so maybe there is a similar issue?...

...ris Lattner <sabre at nondot.org> >> Signed-off-by: Ramkumar Ramachandra <artagnon at gmail.com> >> --- >> I've probably done something stupid; seems to build correctly, but >> that's all I know. Also, tests are pending. >> >> lib/Target/X86/X86InstrInfo.td | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td >> index f33ae2a..4950674 100644 >> --- a/lib/Target/X86/X86InstrInfo.td >> +++ b/lib/Target/X86/X86InstrInfo.td >> @@ -1971,6...

...st), (STORE_DWORD addr:$dst, VRR128:$src)>; but getting the following error; STORE_DWORD: (st (bitconvert:v32i32 VRR128:{v32i32:v32f32}:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> Included from /PIM/lib/Target/X86/X86.td:832: /lib/Target/X86/X86InstrInfo.td:3166:1: error: In STORE_DWORD: Could not infer all types in pattern! def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst, VRR128:$src), ^ anonymous_4820: /PIM/lib/Target/X86/X86.td:832: /lib/Target/X86/X86InstrInfo.td:3173:1: error: In anonymous_4820: Unrecognized node 'VRR12...

Just for informational purposes on a smaller system (Core 2 Duo MacBook Pro): make none X86.td X86InstrInfo.cpp real 11.568 217% 76.283 177% 34.435 169% user 7.726 141% 70.659 100% 25.608 116% sys 3.234 111% 3.992 100% 6.438 104% make -j2 none X86.td X86InstrInfo.cpp real 7.7346 145% 43.138 100% 25.77 127% user 7.6072 139% 70.414 100% 26.589 121% sys 3.2492 111% 3.984 100% 6.671 107% c...

I tried to add an 'OptForSize' requirement to a pattern in X86InstrSSE.td, but it appears to be ignored. However, the condition was detected when specified as a predicate. So this doesn't work: def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), (VMOVDDUPrm addr: $src)>, *Requires<[OptForSize**]>*; But this does: * let Predicates = [OptForSize]

...ng "llc err.ll -o err.s" generates the error. I'm going to try and isolate even further, but as I'm not sure what I'm looking for I don't know if I'll be successful. Does anybody know what this error means? Cannot emit physreg copy instruction UNREACHABLE executed at X86InstrInfo.cpp:2899! 0 libLLVM-3.3.so 0x00007f9f68ddf642 llvm::sys::PrintStackTrace(_IO_FILE*) + 34 1 libLLVM-3.3.so 0x00007f9f68dde9a9 2 libpthread.so.0 0x00007f9f67a07cb0 3 libc.so.6 0x00007f9f67156425 gsignal + 53 4 libc.so.6 0x00007f9f67159b8b abort + 379 5 libLLVM-3.3.so 0x00007f9f68...

Hi Tim, I'm sorry to bother you again. Since I have met the problem, how to check used registers and avoid clobbering live registers, which you mentioned in the email. I am working in the function X86InstrInfo::storeRegToStackSlot, which is in lib/Target/X86/X86InstrInfo.cpp. And I have an extra problem, may I use MOV64mr and two addReg to set two registers as its arguments? I want to use content of one register as the address to be stored, and content of the other register as the source. Thanks a lot!...

...----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Tom Stellard > Sent: 19 September 2014 01:36 > To: Sanjay Patel > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] predicates vs. requirements [TableGen, > X86InstrInfo.td] > > On Thu, Sep 18, 2014 at 03:25:07PM -0600, Sanjay Patel wrote: > > I tried to add an 'OptForSize' requirement to a pattern in X86InstrSSE.td, > > but it appears to be ignored. However, the condition was detected when > > specified as a predicate. > > &g...

...g the MachineFunctionPass and doing the instrumentation in runOnMachineFunction(). But I do not know how to insert a function call. In my work, I write a special function for a program to be compiled and I need to insert this function after certain instructions whose destination register is esp. In X86InstrInfo.cpp, there are two kinds of call may be useful, namely X86::CALL32r and X86::CALL32m. And in X86InstrInfo.td, there are three, namely call32i, call32m and CallImmAddr. But I do not know how to use them to insert my special function. Besides, I can not find LEAVE instruction in X86InstrInfo.cpp thou...

...t; >> but getting the following error; >> STORE_DWORD: (st (bitconvert:v32i32 VRR128:{v32i32:v32f32}:$src), >> addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> >> Included from /PIM/lib/Target/X86/X86.td:832: >> /lib/Target/X86/X86InstrInfo.td:3166:1: error: In STORE_DWORD: Could not >> infer all types in pattern! >> def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst, >> VRR128:$src), >> ^ >> anonymous_4820: /PIM/lib/Target/X86/X86.td:832: >> /lib/Target/X86/X86InstrInfo.td:3173:1:...

...; generates the error. > > I'm going to try and isolate even further, but as I'm not sure what I'm > looking for I don't know if I'll be successful. Does anybody know what > this error means? > > Cannot emit physreg copy instruction > UNREACHABLE executed at X86InstrInfo.cpp:2899! > 0 libLLVM-3.3.so 0x00007f9f68ddf642 > llvm::sys::PrintStackTrace(_IO_FILE*) + 34 > 1 libLLVM-3.3.so 0x00007f9f68dde9a9 > 2 libpthread.so.0 0x00007f9f67a07cb0 > 3 libc.so.6 0x00007f9f67156425 gsignal + 53 > 4 libc.so.6 0x00007f9f67159b8b abort + 379 &...