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2008 Sep 26
0
[LLVMdev] Determining the register type of a MachineOperand
...if I
am only dealing with 32 bit vector registers, I can add write/read masks
that tell the underlying hardware not to work on the whole register, but
just a subset of the components.
32bit scalar mov: mov r1.x___, r0.x000
64bit scalar mov: mov r1.xy__, r0.xy00
96bit scalar mov: mov r1.xyz_, r0.xyz0
128bit scalar mov: mov r1, r0
If I had the register type information at code generation time, then I
can use the exact same tablegen pattern for all my register types and
would only need to add the write/read masks in the printer instead of
multiple patterns.
Multiply this by over 100 opcodes and...
2008 Sep 26
2
[LLVMdev] Determining the register type of a MachineOperand
On Wednesday 24 September 2008 15:23, Mon Ping Wang wrote:
> To my knowledge, I don't think there is an easy way to get the MVT
> information from a MachineOperand. Why do you need it for? In my
See the thread I started on this very topic. Spilling is one place you'd like
to have this information.
> mind, the MachineInstr and its associated operands represent a
>
2011 Mar 31
3
[LLVMdev] Assert in VerifySDNode
We are syncing to 2.9 and we are hitting an with our backend in VerifySDNode in SelectionDAG.cpp.
The first assert here is failing
assert(!isa<MemSDNode>(N) && "Bad MemSDNode!");
Now, this is new to 2.9 and I am trying to understand what is invalid about what I am generating.
What I generate has worked fine from LLVM version 2.4 until now without causing any issues.