Displaying 7 results from an estimated 7 matches for "xsmaddadp".
2017 May 30
2
Pseudo-instruction that overwrites its input register
...loads/stores).
> For example: the definition of LBZU and friends in lib/Target/PowerPC/PPCInstrInfo.td.
> For a simpler example of just the `RegConstraint` usage (as it doesn't use a compound
> node like PPC's address nodes), you can look at all the fused multiply-add such as
> XSMADDADP in lib/Target/PowerPC/PPCInstrVSX.td.
>
> Hope this helps.
Thanks!
However, none of the NoEncode examples in PPCInstrInfo.td seem to have an
isel pattern; and the VSX examples, like XSMADDADP, seem to match on
setting a single output:
let BaseName = "XSMADDADP" in {
let...
2017 May 28
2
Pseudo-instruction that overwrites its input register
On Sun, 28 May 2017, David Chisnall wrote:
>> let Constraints = "@earlyclobber $reg" in
>> def LDWRdPtr : Pseudo<(outs DREGS:$reg),
>> (ins PTRREGS:$ptrreg),
>> "ldw\t$reg, $ptrreg",
>> [(set i16:$reg, (load i16:$ptrreg))]>,
>>
2017 May 30
1
Pseudo-instruction that overwrites its input register
...efinition of LBZU and friends in
>> lib/Target/PowerPC/PPCInstrInfo.td.
>> For a simpler example of just the `RegConstraint` usage (as it doesn't
>> use a compound
>> node like PPC's address nodes), you can look at all the fused
>> multiply-add such as
>> XSMADDADP in lib/Target/PowerPC/PPCInstrVSX.td.
>>
>> Hope this helps.
>>
>
> Thanks!
>
> However, none of the NoEncode examples in PPCInstrInfo.td seem to have an
> isel pattern; and the VSX examples, like XSMADDADP, seem to match on
> setting a single output:
>
>...
2016 Mar 16
2
[VSXFMAMutate] OldFMAReg may be wrongly rewritten
I implemented a proof of concept of a new generic MachineFunction SSA pass.
The code is not readable and not efficient yet, but it shows interesting
results:
In fma.ll @test_FMSUB2 (return dummy(A * B + C, A * B - D)):
before:
fmr 0, 1
xsmaddadp 3, 0, 2
xsmsubmdp 0, 2, 4
fmr 1, 3
fmr 2, 0
bl dummy2
after:
xsmsubadp 4, 1, 2
xsmaddmdp 1, 2, 3
fmr 2, 4
bl dummy2
In fma-assoc.ll all 9 copies are eliminated, for example (A * B + C * D +
E):
before:
xsmaddmdp 3, 4, 5...
2016 Mar 23
0
[VSXFMAMutate] OldFMAReg may be wrongly rewritten
...wrote:
> I implemented a proof of concept of a new generic MachineFunction SSA
> pass. The code is not readable and not efficient yet, but it shows
> interesting results:
>
> In fma.ll @test_FMSUB2 (return dummy(A * B + C, A * B - D)):
> before:
> fmr 0, 1
> xsmaddadp 3, 0, 2
> xsmsubmdp 0, 2, 4
> fmr 1, 3
> fmr 2, 0
> bl dummy2
>
> after:
> xsmsubadp 4, 1, 2
> xsmaddmdp 1, 2, 3
> fmr 2, 4
> bl dummy2
>
> In fma-assoc.ll all 9 copies are eliminated, for example (A...
2016 Mar 05
2
[VSXFMAMutate] OldFMAReg may be wrongly rewritten
I wonder if we can do this in a separate analysis MachineFunction SSA pass.
1) SelectionDAG will generate a pseudo instruction MutatingFMA. When it's
generated it's allowed to have d = a * b + c form, where d doesn't have to
be in {a, b, c}.
2) Later, the proposed pass uses an algorithm to decide for instruction MI:
`%vreg0 = MutatingFMA %vreg1, %vreg2, %vreg3`, it should tie %vreg0
2020 Aug 25
3
[TableGen] What to do if there are overlapping instruction patterns?
I've been working on adding support for a (semi-proprietary) extension
for PowerPC called "Paired-Singles". It's a SIMD instruction set
supporting various operations on a vector of 2 32-bit floating point
numbers.
The Extension is found in the PowerPC 750CL, modified variants of it are
used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and
the Nintendo Wii U