search for: xchg_rr

Hi, guys, What is the opcode of the instruction to swap two registers in X86? After updating my LLVM branch, I realized that there is no longer an opcode for xchg with two register operands in X86GenInstrNames.inc. I found only instructions to swap memory and registers: XCHG16rm, XCHG32rm, XCHG64rm and XCHG8rm. I am updating from LLVM 2.1 to current trunk. The names that I was

On Jul 20, 2008, at 11:50 AM, Fernando Magno Quintao Pereira wrote: > I am updating from LLVM 2.1 to current trunk. The names that I was > using > in LLVM 2.1 were: XCHG8rr, XCHG16rr, XCHG32rr and XCHG64rr. > > Ps.: Evan, thank you for answering the question about IMPLICIT_DEF's. I think they were removed just because noone was using them. Also, the JIT encoding may have

I was using them to do SSA-elimination after register allocation. I can implement swaps using three XOR's, but then the code becomes a little bigger and slower. I think even for the sake of completeness, the X86 back-end should offer the possibility of swapping two registers with one single instruction. Do you guys think there is any possibility that those instructions could come back to