Displaying 4 results from an estimated 4 matches for "xchg8rr".
2008 Jul 20
2
[LLVMdev] What happened to XCHG_rr?
...I realized that there is no longer an
opcode for xchg with two register operands in X86GenInstrNames.inc. I
found only instructions to swap memory and registers: XCHG16rm, XCHG32rm,
XCHG64rm and XCHG8rm.
I am updating from LLVM 2.1 to current trunk. The names that I was using
in LLVM 2.1 were: XCHG8rr, XCHG16rr, XCHG32rr and XCHG64rr.
Ps.: Evan, thank you for answering the question about IMPLICIT_DEF's.
All the best,
Fernando
2008 Jul 20
0
[LLVMdev] What happened to XCHG_rr?
On Jul 20, 2008, at 11:50 AM, Fernando Magno Quintao Pereira wrote:
> I am updating from LLVM 2.1 to current trunk. The names that I was
> using
> in LLVM 2.1 were: XCHG8rr, XCHG16rr, XCHG32rr and XCHG64rr.
>
> Ps.: Evan, thank you for answering the question about IMPLICIT_DEF's.
I think they were removed just because noone was using them. Also,
the JIT encoding may have not been correct, I don't recall.
-Chris
2007 Jul 03
2
[LLVMdev] Swaps of FP registers
...,
unsigned r2,
const TargetRegisterClass *rc
) const {
unsigned Opc;
if (rc == &X86::GR32RegClass) {
Opc = X86::XCHG32rr;
} else if (rc == &X86::GR16RegClass) {
Opc = X86::XCHG16rr;
} else if (rc == &X86::GR8RegClass) {
Opc = X86::XCHG8rr;
} else {
assert(0 && "Unknown regclass in add swap");
abort();
}
BuildMI(mbb, mi, Opc, 1, r1).addReg(r2);
}
thanks,
Fernando
2008 Jul 20
1
[LLVMdev] What happened to XCHG_rr?
...ecomes NP-complete, whereas it is
linear on the size of the interference graph otherwise.
best,
Fernando
> On Jul 20, 2008, at 11:50 AM, Fernando Magno Quintao Pereira wrote:
>> I am updating from LLVM 2.1 to current trunk. The names that I was
>> using
>> in LLVM 2.1 were: XCHG8rr, XCHG16rr, XCHG32rr and XCHG64rr.
>>
>> Ps.: Evan, thank you for answering the question about IMPLICIT_DEF's.
>
> I think they were removed just because noone was using them. Also,
> the JIT encoding may have not been correct, I don't recall.
>
> -Chris
> ____...