Displaying 8 results from an estimated 8 matches for "xacq".
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2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
Here is the patch
0003-Add-XACQ-XREL-prefix-and-encoding-asm-printer-suppor.patch
Yours
- Michael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extens...
2013 Feb 19
9
[LLVMdev] [RFC] Add Intel TSX HLE Support
Hi All,
I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
HLE from Intel TSX [2] is legacy compatible instruction set extension to
specify transactional region by adding XACQUIRE and XRELEASE prefixes.
To support that, GCC chooses the approach by extending the memory order
flag in __atomic_* builtins with target-specific memory model in high
bits (bit 31-16 for target-specific memory model, bit 15-0 for the
general memory model.) To follow the similar approach, I propos...
2013 Feb 19
2
[LLVMdev] [RFC] Add Intel TSX HLE Support
Hi All,
I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to
specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order
flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach, I propos...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
...19, 2013, at 11:52 AM, Michael Liao <michael.liao at intel.com> wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order
> flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach, I p...
2006 Sep 11
2
3.0.23b -> 3.0.23c
I portupgraded my working 3.0.23b PDC on FreeBSD 5.5 to 3.0.23c and found
that all workstations could not login. The log file reads:
get_md4pw: Workstation PC01$: no account in domain
I ran pdbedit -L, and it returned nothing. I use tdbsam backend; all user
accounts show up fine with 3.0.23b. Now they are missing. I deinstalled
3.0.23c and switched back to 3.0.23b. Everything is then back
2013 Feb 28
1
[LLVMdev] [RFC] Add Intel TSX HLE Support
..., Michael Liao <michael.liao at intel.com> wrote:
>
>> Hi All,
>>
>> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to
>> specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order
>> flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach,...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
...Yours
- Michael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes.
> To support that, GCC chooses the approach by extending the memory order
> flag in __atomic_* builtins with target-specific memory model in high
> bits (bit 31-16 for target-specific memory model, bit 15-0 for the
> general memory model.) To follow the simila...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
...Yours
- Michael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes.
> To support that, GCC chooses the approach by extending the memory order
> flag in __atomic_* builtins with target-specific memory model in high
> bits (bit 31-16 for target-specific memory model, bit 15-0 for the
> general memory model.) To follow the simila...