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...t; | R -d "/home/a215020/Bin/bin/valgrind --tool=memcheck --leak-check=full" --vanilla --slave --args $*; exit unlink("/tmp/myddp1", recursive=TRUE) unlink("/tmp/myddp2", recursive=TRUE) gctorture(TRUE) require(g.data) y <- list() s <- list(tgt="ABCDE", acq="FGHIJ", rat=1, cash=0, stdt=20051031) acq.dvd <- tgt.dvd <- NULL dts <- c(20051031,20051101,20051102,20051103,20051104,20051107,20051108,2005110 9,20051110) g.data.attach("/tmp/myddp1") assign("id.ric", c("ABCDE","FGHIJ", letters[1:16]),...

...T1 (S1 )stores to a location l as non-atomic, T2 then (S2)stores to l as SC-atomic, later T3 (L3)loads from l as SC-atomic. I think the load @ T3 should return undef, since it can see both writes from T1 T2. Then the question is if the SC store @ T2 --- S2 and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) edge. This will affect if later conflicting accesses are ordered or not, and whether memory accesses are ordered makes load return undef or not. If the S2 and L3 still introduces an SW edge, the next question is suppose there is a later SC-load L3' @ T3, does it also r...

...Save As to save a file on disk or to extract data to a file on disk and the network software did not update the directory. Reconfigure the network so that directory updates are not deferred. If the user owns the file, they do not get this message. I am using 18p4 and the share is defined as: [acq] comment = Share for acq browsable = yes path = /home/goober/acq/share read only = no fake directory create times = True create mode = 770 locking = no I put in fake directory create times because it sounded like it might fix the problem but it didn't. Any suggestions/co...

...l as non-atomic, > T2 then (S2)stores to l as SC-atomic, > later T3 (L3)loads from l as SC-atomic. > > I think the load @ T3 should return undef, since it can see both > writes from T1 T2. Then the question is if the SC store @ T2 --- S2 > and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) > edge. > > This will affect if later conflicting accesses are ordered or not, and > whether memory accesses are ordered makes load return undef or not. > > If the S2 and L3 still introduces an SW edge, the next question is > suppose there is a later SC-...

...; T2 then (S2)stores to l as SC-atomic, >> later T3 (L3)loads from l as SC-atomic. >> >> I think the load @ T3 should return undef, since it can see both >> writes from T1 T2. Then the question is if the SC store @ T2 --- S2 >> and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) >> edge. >> >> This will affect if later conflicting accesses are ordered or not, and >> whether memory accesses are ordered makes load return undef or not. >> >> If the S2 and L3 still introduces an SW edge, the next question is >>...

...; T2 then (S2)stores to l as SC-atomic, >> later T3 (L3)loads from l as SC-atomic. >> >> I think the load @ T3 should return undef, since it can see both >> writes from T1 T2. Then the question is if the SC store @ T2 --- S2 >> and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) >> edge. >> >> This will affect if later conflicting accesses are ordered or not, and >> whether memory accesses are ordered makes load return undef or not. >> >> If the S2 and L3 still introduces an SW edge, the next question is >>...

...to l as SC-atomic, >>> later T3 (L3)loads from l as SC-atomic. >>> >>> I think the load @ T3 should return undef, since it can see both >>> writes from T1 T2. Then the question is if the SC store @ T2 --- S2 >>> and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) >>> edge. >>> >>> This will affect if later conflicting accesses are ordered or not, and >>> whether memory accesses are ordered makes load return undef or not. >>> >>> If the S2 and L3 still introduces an SW edge, the ne...

...>>>> later T3 (L3)loads from l as SC-atomic. >>>> >>>> I think the load @ T3 should return undef, since it can see both >>>> writes from T1 T2. Then the question is if the SC store @ T2 --- S2 >>>> and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) >>>> edge. >>>> >>>> This will affect if later conflicting accesses are ordered or not, and >>>> whether memory accesses are ordered makes load return undef or not. >>>> >>>> If the S2 and L3 still intro...

Hi all, When the 'Originate' command is issued with 'Async' open set to 'yes', I got the response right away with the correct 'ActionID'. What follows is the 'Newchannel' event with a 'Channel' ID, but their is no 'ActionID' to tie it back to the command. How do you guys deal with this? -------------- next part -------------- An HTML

...to l as SC-atomic, >>> later T3 (L3)loads from l as SC-atomic. >>> >>> I think the load @ T3 should return undef, since it can see both >>> writes from T1 T2. Then the question is if the SC store @ T2 --- S2 >>> and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) >>> edge. >>> >>> This will affect if later conflicting accesses are ordered or not, and >>> whether memory accesses are ordered makes load return undef or not. >>> >>> If the S2 and L3 still introduces an SW edge, the ne...

...>>>> later T3 (L3)loads from l as SC-atomic. >>>> >>>> I think the load @ T3 should return undef, since it can see both >>>> writes from T1 T2. Then the question is if the SC store @ T2 --- S2 >>>> and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) >>>> edge. >>>> >>>> This will affect if later conflicting accesses are ordered or not, and >>>> whether memory accesses are ordered makes load return undef or not. >>>> >>>> If the S2 and L3 still intro...

...ire need of a fast fourier transformation for me stupid biologist, i.e. I have a heartbeat signal and would like to decompose it into pure sin waves, getting three vectors, one containing the frequencies of the sin waves, one the magnitudes and one the phases (that's what I get from my data acquisition software's FFT function). I'd be very much obliged, if someone could point out which command would do the job in R. Thanks! Wolfgang

...atomics to library helper functions calls. These helpers test for the presence of LSE instructions and dispatch to corresponding sequence of instructions. There are 100 helpers resulting from various combinations of instruction = { cas| swp | ldadd | ldset| ldclr| ldeor }, memory model = { relax, acq, rel, acq_rel } and size = {1, 2, 4 , 8, 16}. I am considering two possibilities: i. Atomic Expand pass: add new AtomicExpansionKind::OutOfLine, and if it was set by target expand atomics to RTLIB libcalls. It will require to add 100 new "standardized" library names to RuntimeLibcalls....

On Mon, Aug 22, 2011 at 2:49 PM, Santosh Nagarakatte <santosh.nagarakatte at gmail.com> wrote: > Hi all, > > I have been trying to understand the use of undef in both sequential > and concurrent programs. > > >From the LLVM Language Reference Manual, I see the following > definition of undef. > "Undef can be used anywhere a constant is expected, and indicates

...'s [how] parameter is intended to be a way to "get the right code" in any situation where that is important for performance (or whatever other) reasons. For example, on ia64: sync AtomicOpBusyWait byte (1,2,3,4,5,....14,15,16) could be codegenned to a tight busyloop using ld.acq, spinning to see if two 8-byte words become exactly 0, while matching sync AtomicOpBusyWait byte (x) instructions in the worker threads code be codegenned to tight ld.acq/cmpxchg.rel busyloops writing 0 bytes into the appropriate places. (Roughly, the idea is that LLVM backends suppor...

...: On RedHat linux, R-1.1, I've gotten far enough to create the graph that shows on the screen with 3 lines, but I have some trouble. Here is the way I created the three "overlaid" graphs: data<-read.table("DataCulture0",header=T,as.is = TRUE) attach(data) tmp1<-plot(acquaint~T,type='l', ylim=c(0,1),ylab="average proportion",xlab="PERIOD",xlim=c(1,6000),lty=1,pch=1,main="") par("new"=TRUE) tmp2<-plot(harmony~T,type='l', ylim=c(0,1),ylab="average proportion",xlab="PERIOD",xlim=c(1,6000),l...

...odel and the itinerary. The itinerary directly models the stages of each pipeline independently. Some backend maintainers may still want to use itineraries if that level of precision is critical [1]. Another option is extending the new model. [2] I will assume that each queue is fully pipelined (4 ACQ ops can be in-flight). Forcing all this information into a single SchedWriteRes def would look like this: def P5600FLD : SchedWriteRes <[P5600UnitAGQ, P5600UnitFP]> { let Latency = 5; // 4 cycle load + 1 cycle FP writeback let NumMicroOps = 2; } This is bad (for an in-order processor)...

This patch set is intended for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops. The binary patch optimization is important on native case because the paravirt_ops overhead can be reduced by converting indirect

This patch set is intended for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops. The binary patch optimization is important on native case because the paravirt_ops overhead can be reduced by converting indirect

This patch set is intended for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops which depends on the patch series I sent out, ia64/pv_ops, xen: more paravirtualization. The binary patch optimization is important on