search for: x86instravx512

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Tom Stellard > Sent: 19 September 2014 01:36 > To: Sanjay Patel > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] predicates vs. requirements [TableGen, > X86InstrInfo.td] > > On Thu, Sep 18, 2014 at 03:25:07PM -0600, Sanjay Patel wrote: >

Hi Alex, I don’t know too much about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need: If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition. It allows a PatFrag be passed into the avx512_gather multiclass definition. Working backwards from here, the actual PatFrags passed into this are things like ‘mgatherv4i32’. These are patterns that match a MaskedGatherSDNode for a partic...

...this SAE stuff soon? > > > Assembler support is in pretty good shape otherwise. I expect that this > will be added as soon as someone really needs it. Help is always welcome ;) > > Yes, I would love to, but do not know where to fix. Seems like I need to work on the lib/Target/X86/X86InstrAVX512.td file to add the missing SAE support? Thanks, Jun -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140626/dca75374/attachment.html>

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure: "llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2153: llvm::TreePatternNode* llvm::TreePattern::ParseTreePattern(llvm::Init*, llvm::StringRef): Assert...

Hello. I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and scatter operations exist for Mips, named LVI and SVI, respectively. Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector instructions) gather and scatter operations? If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it

...> Alex > > > > On 12/11/2016 5:31 AM, Alex Susu wrote: >> Hello. >> Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have >> to say that the definition of the "multiclass avx512_gather" from >> lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. >> >> I currently have some serious problems with TableGen - it gives an assertion failure: >> "llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2153: llvm::TreePatternNode* >> llvm::TreePattern::ParseTreePattern(llvm:...

...ut it doesn't. Best regards, Alex On 12/11/2016 5:31 AM, Alex Susu wrote: > Hello. > Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have > to say that the definition of the "multiclass avx512_gather" from > lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. > > I currently have some serious problems with TableGen - it gives an assertion failure: > "llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2153: llvm::TreePatternNode* > llvm::TreePattern::ParseTreePattern(llvm::Init*, llvm::St...

On Thu, Jun 26, 2014 at 5:47 AM, Adam Nemet <anemet at apple.com> wrote: > Hi Jun, > > On Jun 25, 2014, at 8:14 AM, Jun Koi <junkoi2004 at gmail.com> wrote: > > > Hi, > > > > I am trying to assemble below instruction with latest LLVM code, but > fail. Am I doing something wrong, or is this a bug? > > > > > > $ echo "vaddps zmm7

Thank you. i understood how avx512 vector instructions are written in x86instravx512. i need to define my vector instructions so i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))],...

...>>> Change the i32 in the store pattern to v64i32. >>> >>> On Fri, Jul 7, 2017 at 8:41 PM hameeza ahmed <hahmed2305 at gmail.com> >>> wrote: >>> >>>> Thank you. i understood how avx512 vector instructions are written in >>>> x86instravx512. i need to define my vector instructions so i wrote; >>>> >>>> def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins >>>> i32mem:$src), >>>> "vmov_256B_rm\t{$src, $dst|$dst, $src}", >>>>...

...gt;>>>>>> hahmed2305 at gmail.com> wrote: >>>>>>>>>>>>> >>>>>>>>>>>>>> Thank you. i understood how avx512 vector instructions are >>>>>>>>>>>>>> written in x86instravx512. i need to define my vector instructions so i >>>>>>>>>>>>>> wrote; >>>>>>>>>>>>>> >>>>>>>>>>>>>> def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), >>>&...