search for: x86_vendor

...TOH, its trivial, and perhaps unlikely to be used again. the problem manifested in the commented out statement. its also worth noting that when offending code is restored, I get this value out Vendor : ?????????????????????????????????? with replacement code: strlcpy(cpu->model, c->x86_vendor_id, sizeof(cpu->vendor)); I get "" void set_generic_info(struct cpuinfo_x86 *c, s_cpu * cpu) { clock_t et = times(NULL); printf("sizeof(cpu->vendor): %d\n", sizeof(cpu->vendor)); printf("sizeof(cpu->model): %d\n", sizeof(cpu->model));...

...TOH, its trivial, and perhaps unlikely to be used again. the problem manifested in the commented out statement. its also worth noting that when offending code is restored, I get this value out Vendor : ?????????????????????????????????? with replacement code: strlcpy(cpu->model, c->x86_vendor_id, sizeof(cpu->vendor)); I get "" void set_generic_info(struct cpuinfo_x86 *c, s_cpu * cpu) { clock_t et = times(NULL); printf("sizeof(cpu->vendor): %d\n", sizeof(cpu->vendor)); printf("sizeof(cpu->model): %d\n", sizeof(cpu->model));...

...struct cpuinfo_x86 *c = &current_cpu_data; if ( (power = processor_powers[smp_processor_id()]) == NULL ) goto default_halt; @@ -601,6 +602,23 @@ static void acpi_dead_idle(void) mb(); __mwait(cx->address, 0); } + } + else if ( c->x86_vendor == X86_VENDOR_AMD && + cx->entry_method == ACPI_CSTATE_EM_SYSIO ) + { + /* Intel prefers not to use SYSIO */ + + /* Avoid references to shared data after the cache flush */ + u32 address = cx->address; + u32 pmtmr_ioport_local = pmtmr_iopor...

Debian bug 812166[0] reported this build failure due to Wmisleading-indentation with gcc-6: non-fatal.c: In function 'init_nonfatal_mce_checker': non-fatal.c:103:2: error: statement is indented as if it were guarded by... [-Werror=misleading-indentation] switch (c->x86_vendor) { ^~~~~~ non-fatal.c:97:5: note: ...this 'if' clause, but it is not if ( __get_cpu_var(poll_bankmask) == NULL ) ^~ I was unable to reproduce (xen builds cleanly for me with "6.0.0 20160117 (experimental) [trunk revision 232481]") but looking at the code the issue ab...

There has been some progress, but still no joy. Definitely not intended for inclusion at this point. Tim, Wei, I added a Xen command line toggle to disable IOMMU and P2M table sharing. Tim, I verified that changes to p2m-pt.c don''t break shadow mode (64bit hypervisor and Win 7 guest). Hongkaixing, I incorporated your suggestion in patch 2, so I should add your Signed-off-by eventually.

https://access.redhat.com/support/policy/intel shows mainly Xeon CPUs. What about Intel Core i7-6700 Quad-Core Skylake has the current EL6 variant support for it? Any experience? Feedback would be greatly appreciated. Thanks, LF

...ged, 10 insertions(+), 2 deletions(-) diff --git a/com32/gplinclude/cpuid.h b/com32/gplinclude/cpuid.h index 02f3a0b3..fd77b69d 100644 --- a/com32/gplinclude/cpuid.h +++ b/com32/gplinclude/cpuid.h @@ -187,8 +187,9 @@ extern bool get_cpu_flag_value_from_name(s_cpu *cpu, const char * flag); #define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 #define X86_VENDOR_NSC 8 -#define X86_VENDOR_UNKNOWN 9 -#define X86_VENDOR_NUM 10 +#define X86_VENDOR_HYGON 9 +#define X86_VENDOR_UNKNOWN 10 +#define X86_VENDOR_NUM 11 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) diff --...

...xen/arch/x86/traps.c Tue Feb 17 22:29:38 2009 +0800 +++ b/xen/arch/x86/traps.c Wed Feb 25 11:23:01 2009 +0800 @@ -2187,10 +2187,17 @@ static int emulate_privileged_op(struct case MSR_IA32_MPERF: case MSR_IA32_APERF: case MSR_IA32_PERF_CTL: + if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ) + goto fail; + if ( !is_cpufreq_controller(v->domain) ) + break; + if ( wrmsr_safe(regs->ecx, eax, edx) != 0 ) + goto fail; + break; case MSR_IA32_THERM_CONTROL: if ( boot...

...a/drivers/xen/core/smpboot.c Fri Feb 29 10:29:13 2008 +0000 +++ b/drivers/xen/core/smpboot.c Fri Feb 29 12:54:47 2008 -0600 @@ -276,7 +276,8 @@ void __init smp_prepare_cpus(unsigned in cpu_2_logical_apicid[0] = 0; x86_cpu_to_apicid[0] = 0; - set_x86_acpiid_to_apicid(0, 0); + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + set_x86_acpiid_to_apicid(0, 0); current_thread_info()->cpu = 0; @@ -325,7 +326,8 @@ void __init smp_prepare_cpus(unsigned in cpu_2_logical_apicid[cpu] = cpu; x86_cpu_to_apicid[cpu] = cpu; - set_x86_acpiid_to_apicid(cpu, cpu); + if (boot_cpu_data.x86_vendor =...

...tel Core i7-6700 Quad-Core Skylake >> >> has the current EL6 variant support for it? >> >> Any experience? Feedback would be greatly appreciated. > > > I found this > > linux-2.6.32-696.1.1.el6/arch/x86/kernel/setup.c > > 796 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && > 797 ((boot_cpu_data.x86 == 6))) { > 798 switch (boot_cpu_data.x86_model) { > 799 case 94: /* Skylake-S */ > 800 case 86: /* Broadwell-DE SoC */ > 801 case 85: /* Purley */ > 802 case 79: /* Broadwell...

...err = cstate_init(); diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 7012d18bb293..3f6d8b5672d5 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1383,7 +1383,7 @@ static int __init intel_uncore_init(void) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return -ENODEV; - if (cpu_has_hypervisor) + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) return -ENODEV; max_packages = topology_max_packages(); diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index fee7a6efcd2d..3aea54ecabfd 100644 -...

...err = cstate_init(); diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 7012d18bb293..3f6d8b5672d5 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1383,7 +1383,7 @@ static int __init intel_uncore_init(void) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return -ENODEV; - if (cpu_has_hypervisor) + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) return -ENODEV; max_packages = topology_max_packages(); diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index fee7a6efcd2d..3aea54ecabfd 100644 -...

These two patches provide the neccessary infrastructure changes for the processor-passthru driver [www.spinics.net/lists/linux-acpi/msg34655.html] to properly function. The first one is quite easy - we just modprobe the processor-passthru driver. The second allows it to work under AMD machines by exposing the PM RDMSR to dom0. It has been tested with 2.6.32 kernel as well to make sure it does

From: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Hi all, This series adds a new microcode driver for Xen. The Xen hypervisor can deal with all the low-level details of doing a microcode update (Intel vs AMD, doing all the physical CPUs present on the system, current and future, etc), so all the driver has to do is make a hypercall to upload the microcode into Xen. This only

The first patch really isn''t as much of a follow-up than what triggered the security issues to be noticed in the first place. 1: x86: preserve FPU selectors for 32-bit guest code 2: x86: fix XCR0 handling 3: x86/xsave: adjust state management 4: x86/fxsave: bring in line with recent xsave adjustments The first two I would see as candidates for 4.3 (as well as subsequent backporting,

...an bug 812166[0] reported this build failure due to > Wmisleading-indentation with gcc-6: > > non-fatal.c: In function 'init_nonfatal_mce_checker': > non-fatal.c:103:2: error: statement is indented as if it were guarded by... [-Werror=misleading-indentation] > switch (c->x86_vendor) { > ^~~~~~ > > non-fatal.c:97:5: note: ...this 'if' clause, but it is not > if ( __get_cpu_var(poll_bankmask) == NULL ) > ^~ > > I was unable to reproduce (xen builds cleanly for me with "6.0.0 20160117 > (experimental) [trunk revision 232481]"...

...O9ieGnyQ$ Please get your IT department to remove that stupidity. If you can't, please send email from a non-Red Hat email address. I don't understand why this is a useful warning to fix. What actual problem is caused by the code below? > return and break > > switch (c->x86_vendor) { > case X86_VENDOR_INTEL: > intel_p5_mcheck_init(c); > return 1; > - break; Sure, it's unnecessary, but it's not masking a bug. It's not unclear. Why do we want to enable this warning?

...ged, 10 insertions(+), 2 deletions(-) diff --git a/com32/gplinclude/cpuid.h b/com32/gplinclude/cpuid.h index 02f3a0b3..fd77b69d 100644 --- a/com32/gplinclude/cpuid.h +++ b/com32/gplinclude/cpuid.h @@ -187,8 +187,9 @@ extern bool get_cpu_flag_value_from_name(s_cpu *cpu, const char * flag); #define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 #define X86_VENDOR_NSC 8 -#define X86_VENDOR_UNKNOWN 9 -#define X86_VENDOR_NUM 10 +#define X86_VENDOR_HYGON 9 +#define X86_VENDOR_UNKNOWN 10 +#define X86_VENDOR_NUM 11 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) diff --...

...; shows mainly Xeon CPUs. What about > > Intel Core i7-6700 Quad-Core Skylake > > has the current EL6 variant support for it? > > Any experience? Feedback would be greatly appreciated. I found this linux-2.6.32-696.1.1.el6/arch/x86/kernel/setup.c 796 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 797 ((boot_cpu_data.x86 == 6))) { 798 switch (boot_cpu_data.x86_model) { 799 case 94: /* Skylake-S */ 800 case 86: /* Broadwell-DE SoC */ 801 case 85: /* Purley */ 802 case 79: /* Broadwell-EP and EX */ 803...

...x86_mcinfo_add(struct mc_info *mi, return buf; } +static void x86_mcinfo_apei_save( + struct mcinfo_global *mc_global, struct mcinfo_bank *mc_bank) +{ + struct mce m; + + memset(&m, 0, sizeof(struct mce)); + + m.cpu = mc_global->mc_coreid; + m.cpuvendor = boot_cpu_data.x86_vendor; + m.cpuid = cpuid_eax(1); + m.socketid = mc_global->mc_socketid; + m.apicid = mc_global->mc_apicid; + + m.mcgstatus = mc_global->mc_gstatus; + m.status = mc_bank->mc_status; + m.misc = mc_bank->mc_misc; + m.addr = mc_bank->mc_addr; + m.bank = mc_bank->m...