Displaying 6 results from an estimated 6 matches for "x86_feature_lm".
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x86_feature_de
2006 Aug 28
2
Extending dmitest to check for Long Mode (aka 64 versus 32 bit)
...hat EDX and EAX means is zero... but
looking through your code I suspect that this may be the missing entry from
the cpu_flags_strings table in dmi_processor.h:
NULL, /* 30 */
In the Linux kernel I see that /proc/cpuinfo is determined through the
/usr/include/asm/cpufeature.h include as:
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
Would I simply need to Change the NULL entry to a string in
cpu_flags_strings table, add a bool in s_cpu_flags and then
dmi.c would automagically set the boolean correctly ?
I could then modify dmitest to check for Long Mode and achieve
my goal.
Any he...
2007 Aug 09
0
[PATCH] x86/hvm: miscellaneous CPUID handling changes
...; 31, edx);
+ __clear_bit(X86_FEATURE_NX & 31, edx);
#ifdef __i386__
/* Mask feature for Intel ia32e or AMD long mode. */
- clear_bit(X86_FEATURE_LAHF_LM & 31, ecx);
+ __clear_bit(X86_FEATURE_LAHF_LM & 31, ecx);
- clear_bit(X86_FEATURE_LM & 31, edx);
- clear_bit(X86_FEATURE_SYSCALL & 31, edx);
+ __clear_bit(X86_FEATURE_LM & 31, edx);
+ __clear_bit(X86_FEATURE_SYSCALL & 31, edx);
#endif
+ break;
}
}
}
Index: 2007-08-08/xen/arch/x86/hvm/svm/svm.c
=============...
2007 Feb 01
0
[PATCH] hide RDTSCP feature flag from PV guests
...cpufeature.h 2007-02-01 17:25:15.000000000 +0100
@@ -49,6 +49,7 @@
#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
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2007 Aug 09
1
[PATCH] svm: allow guest to use EFER.FFXSE and EFER.LMSLE
...X86_FEATURE_MP (1*32+19) /* MP Capable. */
#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_FFXSR (1*32+25) /* FFXSR instruction optimizations */
#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
@@ -93,7 +94,6 @@
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVME...
2008 May 06
4
[PATCH] fixup 3dnow! support
...cpuid(struct kvm_vcpu *vcpu,
vcpu->arch.cpuid_entries[i].padding[2] = 0;
}
vcpu->arch.cpuid_nent = cpuid->nent;
- cpuid_fix_nx_cap(vcpu);
+ cpuid_fix_caps(vcpu);
r = 0;
out_free:
@@ -1061,8 +1075,8 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
bit(X86_FEATURE_LM) |
#endif
bit(X86_FEATURE_MMXEXT) |
- bit(X86_FEATURE_3DNOWEXT) |
- bit(X86_FEATURE_3DNOW);
+ (bit(X86_FEATURE_3DNOWEXT) && cpu_has_3dnowext) |
+ (bit(X86_FEATURE_3DNOW) && cpu_has_3dnow);
const u32 kvm_supported_word3_x86_features =
bit(X86_FEATURE_XMM3) | bit(X86_FEAT...
2008 May 06
4
[PATCH] fixup 3dnow! support
...cpuid(struct kvm_vcpu *vcpu,
vcpu->arch.cpuid_entries[i].padding[2] = 0;
}
vcpu->arch.cpuid_nent = cpuid->nent;
- cpuid_fix_nx_cap(vcpu);
+ cpuid_fix_caps(vcpu);
r = 0;
out_free:
@@ -1061,8 +1075,8 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
bit(X86_FEATURE_LM) |
#endif
bit(X86_FEATURE_MMXEXT) |
- bit(X86_FEATURE_3DNOWEXT) |
- bit(X86_FEATURE_3DNOW);
+ (bit(X86_FEATURE_3DNOWEXT) && cpu_has_3dnowext) |
+ (bit(X86_FEATURE_3DNOW) && cpu_has_3dnow);
const u32 kvm_supported_word3_x86_features =
bit(X86_FEATURE_XMM3) | bit(X86_FEAT...