Displaying 20 results from an estimated 78 matches for "x86_capability".
2010 Sep 17
2
Constant vs Nonstop vs Invariant TSC question
>From /xen-unstable.hg/xen/arch/x86/cpu/intel.c
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
if (cpuid_edx(0x80000007) & (1u<<8)) {
set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
}
I am trying to determine the difference between the constant vs non...
2007 Apr 18
0
[PATCH 2/2] x86: clean up identify_cpu
...lly picking apart the CPU stuff...
*/
-void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
+static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
{
int i;
@@ -486,30 +486,43 @@ void __cpuinit identify_cpu(struct cpuin
for (i = 0; i < NCAPINTS; i++)
printk(" %08lx", c->x86_capability[i]);
printk("\n");
-
+}
+
+void __init identify_boot_cpu(void)
+{
+ identify_cpu(&boot_cpu_data);
+
+ /* Init Machine Check Exception if available. */
+ mcheck_init(&boot_cpu_data);
+
+ sysenter_setup();
+ enable_sep_cpu();
+
+ mtrr_bp_init();
+}
+
+void __cpuinit identify_secon...
2007 Apr 18
0
[PATCH 2/2] x86: clean up identify_cpu
...lly picking apart the CPU stuff...
*/
-void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
+static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
{
int i;
@@ -486,30 +486,43 @@ void __cpuinit identify_cpu(struct cpuin
for (i = 0; i < NCAPINTS; i++)
printk(" %08lx", c->x86_capability[i]);
printk("\n");
-
+}
+
+void __init identify_boot_cpu(void)
+{
+ identify_cpu(&boot_cpu_data);
+
+ /* Init Machine Check Exception if available. */
+ mcheck_init(&boot_cpu_data);
+
+ sysenter_setup();
+ enable_sep_cpu();
+
+ mtrr_bp_init();
+}
+
+void __cpuinit identify_secon...
2011 May 30
6
[PATCH] CPUID level 0x00000007:0 (ebx) is word 9, instead of word 7
.../
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
-#define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
+#define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
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2013 Nov 11
2
[PATCH] x86/Intel: don't probe CPUID faulting on family 0xf CPUs
...u/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -204,7 +204,7 @@ static void __devinit init_intel(struct
detect_ht(c);
}
- if (smp_processor_id() == 0) {
+ if (c == &boot_cpu_data && c->x86 == 6) {
if (probe_intel_cpuid_faulting())
set_bit(X86_FEATURE_CPUID_FAULTING, c->x86_capability);
} else if (boot_cpu_has(X86_FEATURE_CPUID_FAULTING)) {
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2007 Apr 18
7
[patch 0/6] Various cleanups
Hi Andi,
Here's a little batch of cleanups:
- re-enable VDSO when PARAVIRT is enabled
- make the parainstructions symbols match the
other altinstructions naming convention
- add kernel command-line options to disable altinstructions for
smp and pv_ops
Oh, and I'm mailing your noreplacement patch back at you, for no
particularly good reason.
J
--
2007 Apr 18
7
[patch 0/6] Various cleanups
Hi Andi,
Here's a little batch of cleanups:
- re-enable VDSO when PARAVIRT is enabled
- make the parainstructions symbols match the
other altinstructions naming convention
- add kernel command-line options to disable altinstructions for
smp and pv_ops
Oh, and I'm mailing your noreplacement patch back at you, for no
particularly good reason.
J
--
2020 May 20
2
[PATCH v3 64/75] x86/sev-es: Cache CPUID results for improved performance
...ms like overkill. The number of CPUID
leaves that are invoked after boot with any regularity can probably be counted
on one hand. IIRC glibc invokes CPUID to gather TLB/cache info, XCR0-based
features, and one or two other leafs. A statically sized global array that's
arbitrarily index a la x86_capability would be just as simple and more
performant. It would also allow fancier things like emulating CPUID 0xD in
the guest if you want to go down that road.
2020 May 20
2
[PATCH v3 64/75] x86/sev-es: Cache CPUID results for improved performance
...ms like overkill. The number of CPUID
leaves that are invoked after boot with any regularity can probably be counted
on one hand. IIRC glibc invokes CPUID to gather TLB/cache info, XCR0-based
features, and one or two other leafs. A statically sized global array that's
arbitrarily index a la x86_capability would be just as simple and more
performant. It would also allow fancier things like emulating CPUID 0xD in
the guest if you want to go down that road.
2010 Oct 07
0
[PATCH] x86-64: workaround for BIOSes wrongly enabling LAHF_LM feature indicator
...return err;
+}
+
/*
* Mask the features and extended features returned by CPUID. Parameters are
* set from the boot line via two methods:
@@ -329,6 +370,24 @@ static void __devinit init_amd(struct cp
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
clear_bit(0*32+31, c->x86_capability);
+#ifdef CONFIG_X86_64
+ if (c->x86 == 0xf && c->x86_model < 0x14
+ && cpu_has(c, X86_FEATURE_LAHF_LM)) {
+ /*
+ * Some BIOSes incorrectly force this feature, but only K8
+ * revision D (model = 0x14) and later actually support it.
+ * (AMD Erratum #110, docI...
2019 May 15
1
[PATCH] Add support for Hygon Dhyana processor
...lag);
#define X86_VENDOR_RISE 6
#define X86_VENDOR_TRANSMETA 7
#define X86_VENDOR_NSC 8
-#define X86_VENDOR_UNKNOWN 9
-#define X86_VENDOR_NUM 10
+#define X86_VENDOR_HYGON 9
+#define X86_VENDOR_UNKNOWN 10
+#define X86_VENDOR_NUM 11
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
diff --git a/com32/gpllib/cpuid.c b/com32/gpllib/cpuid.c
index 2abd0bda..0681dbce 100644
--- a/com32/gpllib/cpuid.c
+++ b/com32/gpllib/cpuid.c
@@ -60,6 +60,11 @@ static struct cpu_dev amd_cpu_dev = {
.c_ident = {"AuthenticAMD"}
};
+static struct cpu_dev hygon_cpu_dev = {
+ ....
2007 Aug 09
1
[PATCH] svm: allow guest to use EFER.FFXSE and EFER.LMSLE
...in long mode */
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVME (6*32+ 2) /* Secure Virtual Machine */
-#define X86_FEATURE_FFXSR (6*32+25) /* FFXSR instruction optimizations */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
@@ -121,6 +121,7 @@
#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
#define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
+#define cpu_has_f...
2012 Feb 28
3
[Patch] X86: expose HLE/RTM features to dom0
...nd bit manipulation extensions */
#define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */
+#define X86_FEATURE_RTM (7*32+11) /* Restricted Transactional Memory */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
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2011 Jan 21
11
[PATCH]x86:x2apic: Disable x2apic on x86-32 permanently
...el.com>
diff -r 02c0af2bf280 xen/arch/x86/apic.c
--- a/xen/arch/x86/apic.c Mon Jan 17 18:05:52 2011 +0000
+++ b/xen/arch/x86/apic.c Wed Jan 19 03:24:16 2011 -0500
@@ -961,6 +961,22 @@
if ( !cpu_has_x2apic )
return;
+#ifdef __i386__
+ clear_bit(X86_FEATURE_X2APIC, boot_cpu_data.x86_capability);
+ if (x2apic_enabled) {
+ uint64_t msr_content;
+
+ rdmsrl(MSR_IA32_APICBASE, msr_content);
+ msr_content &= ~(MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD);
+ wrmsrl(MSR_IA32_APICBASE, msr_content);
+ msr_content |= MSR_IA32_APICBASE_ENABLE;
+...
2007 Aug 09
0
[PATCH] x86/hvm: miscellaneous CPUID handling changes
...#define X86_FEATURE_3DNOWPF (6*32+ 8) /* 3DNow! Prefetch */
+#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
+#define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
+#define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
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2007 Apr 18
0
[PATCH 4/5] Vmi.patch
...;
+ local_irq_restore(flags & X86_EFLAGS_IF);
+}
+
+static int __init parse_vmi(char *arg)
+{
+ if (!arg)
+ return -EINVAL;
+
+ if (!strcmp(arg, "disable_nodelay"))
+ disable_nodelay = 1;
+ else if (!strcmp(arg, "disable_pge")) {
+ clear_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability);
+ disable_pge = 1;
+ } else if (!strcmp(arg, "disable_pse")) {
+ clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
+ disable_pse = 1;
+ } else if (!strcmp(arg, "disable_sep")) {
+ clear_bit(X86_FEATURE_SEP, boot_cpu_data.x86_capability);
+ disable_sep = 1;
+ } els...
2007 Apr 18
0
[PATCH 4/5] Vmi.patch
...;
+ local_irq_restore(flags & X86_EFLAGS_IF);
+}
+
+static int __init parse_vmi(char *arg)
+{
+ if (!arg)
+ return -EINVAL;
+
+ if (!strcmp(arg, "disable_nodelay"))
+ disable_nodelay = 1;
+ else if (!strcmp(arg, "disable_pge")) {
+ clear_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability);
+ disable_pge = 1;
+ } else if (!strcmp(arg, "disable_pse")) {
+ clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
+ disable_pse = 1;
+ } else if (!strcmp(arg, "disable_sep")) {
+ clear_bit(X86_FEATURE_SEP, boot_cpu_data.x86_capability);
+ disable_sep = 1;
+ } els...
2007 Apr 18
0
[PATCH 5/6] VMI backend for paravirt-ops
...;
+ local_irq_restore(flags & X86_EFLAGS_IF);
+}
+
+static int __init parse_vmi(char *arg)
+{
+ if (!arg)
+ return -EINVAL;
+
+ if (!strcmp(arg, "disable_nodelay"))
+ disable_nodelay = 1;
+ else if (!strcmp(arg, "disable_pge")) {
+ clear_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability);
+ disable_pge = 1;
+ } else if (!strcmp(arg, "disable_pse")) {
+ clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
+ disable_pse = 1;
+ } else if (!strcmp(arg, "disable_sep")) {
+ clear_bit(X86_FEATURE_SEP, boot_cpu_data.x86_capability);
+ disable_sep = 1;
+ } els...
2007 Apr 18
0
[PATCH 5/6] VMI backend for paravirt-ops
...;
+ local_irq_restore(flags & X86_EFLAGS_IF);
+}
+
+static int __init parse_vmi(char *arg)
+{
+ if (!arg)
+ return -EINVAL;
+
+ if (!strcmp(arg, "disable_nodelay"))
+ disable_nodelay = 1;
+ else if (!strcmp(arg, "disable_pge")) {
+ clear_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability);
+ disable_pge = 1;
+ } else if (!strcmp(arg, "disable_pse")) {
+ clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
+ disable_pse = 1;
+ } else if (!strcmp(arg, "disable_sep")) {
+ clear_bit(X86_FEATURE_SEP, boot_cpu_data.x86_capability);
+ disable_sep = 1;
+ } els...
2020 Sep 16
0
[RFC PATCH] x86_64: Add support for Hygon Dhyana processor
...lag);
#define X86_VENDOR_RISE 6
#define X86_VENDOR_TRANSMETA 7
#define X86_VENDOR_NSC 8
-#define X86_VENDOR_UNKNOWN 9
-#define X86_VENDOR_NUM 10
+#define X86_VENDOR_HYGON 9
+#define X86_VENDOR_UNKNOWN 10
+#define X86_VENDOR_NUM 11
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
diff --git a/com32/gpllib/cpuid.c b/com32/gpllib/cpuid.c
index 2abd0bda..0681dbce 100644
--- a/com32/gpllib/cpuid.c
+++ b/com32/gpllib/cpuid.c
@@ -60,6 +60,11 @@ static struct cpu_dev amd_cpu_dev = {
.c_ident = {"AuthenticAMD"}
};
+static struct cpu_dev hygon_cpu_dev = {
+ ....