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...reason is, it may do harm to the source code level debug? Or it involves complicated alias analysis? If I want to do it by myself, any further advice? 2014-10-13 23:32 GMT+08:00 Hal Finkel <hfinkel at anl.gov>: > > ----- Original Message ----- > > From: "Qingan Li" <ww345ww at gmail.com> > > To: llvmdev at cs.uiuc.edu > > Sent: Monday, October 13, 2014 8:29:38 AM > > Subject: [LLVMdev] Problem of stack slot coloring > > > > Hi, > > > > > > Can anyone help me with the stack slot coloring optimization? > > This co...

---------- Forwarded message ---------- From: Qingan Li <ww345ww at gmail.com> Date: 2011/5/30 Subject: To: llvmdev at cs.uiuc.edu Hi, I wrote an analysis pass, myPass, inherited from both ModulePass and ProfileInfo, and this pass requires the CallGraph, i.e., * class myPass : public ModulePass, public ProfileInfo { ...};* * void myPass::getAnalysisUsa...

Hi, Can anyone help me with the stack slot coloring optimization? This corresponding file is /lib/codegen/stackslotcoloring.cpp. It is said this optimization was for stack slot overlay for frame size reduction, after register allocation phase. And this transformation pass relies on the LiveStack analysis pass. How, when checking the source code, it seems the LiveStack analysis has not been

When I searched for branch frequency profiling on the internet, I got this link by a casual chance: http://homepages.dcc.ufmg.br/~rimsa/tools/stprof-llvm.patch. It seems it was written by Andrei Rimsa. So I downloaded and integrate these files into the llvm-2.8 building. After the building, I tried "opt -static-profile bitcnt_1.bc", and an segment fault error occured. I debugged it

Thanks for your last reply. Could I understand the way to adding a pass (built into the llvm rather than dynamic loadable) includes: 1. Declaring a creator function for this pass 2. Implementing the creator function for this pass 3. Instantiating this pass and get a object of it 3. Register this pass into the PassRegistry Then, for a built-into bytecode pass, task 1(declaration of the

---------- Forwarded message ---------- From: Qingan Li <ww345ww at gmail.com> Date: 2011/1/19 Subject: Re: [LLVMdev] About test suits Cont1 To: Eric Christopher <echristo at apple.com> *I am sorry for making you confused when I presented my problem.* *1. My steps for the test suit building:* (1) cd /home/qali/Src; * // This is my source di...

*1. I have searched the access/setting of LLVMCC_EMITIR_FLAG in the build directory, recursively, and all the output is what I pasted in last email (just the same to the that in source directory). Maybe the configure failed to do it. My command list for building the test suit is as followings:* *(1) cd ~/SRC_DIR/llvm/projects* *(2) svn co http://llvm.org/svn/llvm-project/test-suite/trunk

I use a 64bit-x86 computer, with Fedora Core 13, and want to build the llvm-gcc. According to the README.LLVM file, I firstly built llvm 2.8 in /home/qali/install/llvm-2.8 using: $./configure $./make ENABLE_OPTIMIZED=1 It succeded. Then, I tried to built llvm-gcc in an 'obj' directory different from the soucre directory, using: $./llvm-gcc-4.2-2.8.source/configure

Hi, I worked in llvm to get some information from live variable analysis. If the live range of one variable interferes with another, we could record the related two variables into a pair. For example, with a function with local variables 'a', 'b', 'c', 'x' and 'y', the pair set { (a, b), (b,c), (x,y)} indicates that 'a' interferes with 'b',

Hi, Except for the guide in http://llvm.org/docs/Projects.html#help, is there any easier way to get the llvm projects for famous benchmark suits, such as MiBench, SPEC2000, .etc? In other words, is there preconfigured and downloadable llvm projects for famous benchmark suits? -- Best regards, Li Qingan -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi Mr/Mz, I have built and installed llvm-2.8 in debug mode using: >SRC_DIR/configure --prefix=INS_DIR --enable-debug-runtime --disable-optimized --enable-debug-symbols >make install It seems the NDEBUG controls a lot of print-out of debug information, by using DEBUG() or dbgs(). And it is said that NDEBUG is in enabled in debug mode, but I find it does not work and the -debug option

Hi, Thanks for your last reply. Could I understand the way to adding a pass (built into the llvm rather than dynamic loadable) includes: 1. Declaring a creator function for this pass 2. Implementing the creator function for this pass 3. Instantiating this pass and get a object of it 3. Register this pass into the PassRegistry Then, for a built-into bytecode pass, task 1(declaration of

Hi, I want to know what is the type or size of a virtual register in a Machineinstr::MachineOperand (If this MachineOperand is a register). For example, what is the size of reg16385 in the following MachineInstr. I know now in the llvm bitcode, the type of a Instruction could be obtained from the Value::GetType(), but what is the counterpart in MachineInstr (not derived from class Value)?

Hi, I wrote an analysis pass, myPass, inherited from both ModulePass and ProfileInfo, and this pass requires the CallGraph, i.e., * class myPass : public ModulePass, public ProfileInfo { ...};* * void myPass::getAnalysisUsage(AnalysisUsage &AU) const {* * AU.addRequired<CallGraph>();* * AU.setPreservesAll();* *}* Then, I assumes the UnreachableBlockElim (inherited from

The following is the code fragment after "# *** IR Dump Before Prolog/Epilog Insertion & Frame Finalization ***:". * MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 0 * * MOV32mr <fi#2>, 1, %reg0, 0, %reg0, %ECX<kill>* * %EAX<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0* * MOV32mr %reg0, 1, %reg0, <ga:@one+4>, %reg0, %EAX<kill>* * %EAX<def> = MOV32rm

1. My configuration: OS: ubuntu11.04, CPU: Intel(R) Core(TM) i5-2410M CPU @ 2.30GHz llvm: llvm-2.8 2. My running environment: ~#llvm-gcc -DCOMPDATE="today" -DCFLAGS="" -DHOSTNAME="thishost" -DNeedFunctionPrototypes=1 -DSASR -DPROBES=8 -O3 -emit-llvm /home/qali/Develop/Benchmark/MultipleSource/FreeBench/distray/distray.c -o

Hi, I wonder if there is an interface for me to access the type or size of virtual registers in the SSA form? I have scanned the MachineOperand in CodeGen part, and failed to find this kind of info for virtual registers. -- Best regards, Li Qingan -------------- next part -------------- An HTML attachment was scrubbed... URL:

I have tested the register allocation in llvm, using: $llc -debug test.bc where, test.c is like: int a, b, c, d, x; a = 3; b = 5; d = 4; x = 100; if ( a > b ) ...... And I got the machine code before register allocation: MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 3; mem:ST4[%a] MOV32mi <fi#3>, 1, %reg0, 0, %reg0,

I am sorry for my poor statement of my problem. Yes, ��f�� is right. I want to know whether llvm could emit debugging information which GDB could use directly. Ex, how does the executable file generated from llc could be debug using gdb? A simple demonstration is greatly appreciated. 2011/6/14 ��f�� <chenwj at iis.sinica.edu.tw> > > Debug information can be placed in the assembler

I have seen INITIALIZE_PASS(LiveVariables, "livevars", "Live Variable Analysis", false, false); in the llvm/lib/codegen/LiveVariables.cpp, where LiveVariables is a subclass of MachineFunctionPass, and #define INITIALIZE_PASS(passName, arg, name, cfg, analysis) \ static RegisterPass<passName> passName ## _info(arg, name, cfg, analysis) in PassSupport.h Is this code used