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writealu
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
...ruction {
let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>
// schedule info
II_TEST: InstrItinClass;
def ALU1: ProcResource<1>;
def ALU2: ProcResource<1>;
def WriteALU1: SchedWriteRes<[ALU1]> { let Latency = 1; }
def WriteALU2: SchedWriteRes<[ALU2]> { let Latency = 2; }
def : ItinRW<[WriteALU1, WriteALU2], [II_TEST]>
From this example, we can access the latency information of MI with
'getWriteLatencyEntry()' and the resource information of MI with
'getWriteProcResBegin()'. At this point,...