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2016 Nov 22
3
[RFC] Supporting ARM's SVE in LLVM
Hi Renato,
Sorry for the delay in responding. We've been busy rethinking some of our changes after the feedback we've received thus far (particularly from the devmeeting). The incremental patches will use our revised design(which should be less invasive), and I'll be updating our document to match.
On 16/11/2016, 12:46, "Renato Golin" <renato.golin at linaro.org>
2016 Nov 24
2
[RFC] Supporting ARM's SVE in LLVM
...; Constant *StepVectorValue::get(Type *Ty);
> ```
>
> ### Example:
>
> The following shows the construction of a scalable vector of the form
> <start, start-2, start-4, ...>:
>
> ```llvm
> %elt = insertelement <n x 4 x i32> undef, i32 %start, i32 0
> %widestart = shufflevector <n x 4 x i32> %elt, <n x 4 x i32> undef, <n x
> 4 x i32> zeroinitializer
> %step = insertelement <n x 4 x i32> undef, i32 -2, i32 0
> %widestep = shufflevector <n x 4 x i32> %step, <n x 4 x i32> undef, <n x
> 4 x i32> zeroini...
2016 Nov 25
2
[RFC] Supporting ARM's SVE in LLVM
...(from byte to
word, for example), or make the process of doing so more complex.
> The following shows the construction of a scalable vector of the form
> <start, start-2, start-4, ...>:
>
> ```llvm
> %elt = insertelement <n x 4 x i32> undef, i32 %start, i32 0
> %widestart = shufflevector <n x 4 x i32> %elt, <n x 4 x i32> undef, <n x 4 x i32> zeroinitializer
> %step = insertelement <n x 4 x i32> undef, i32 -2, i32 0
> %widestep = shufflevector <n x 4 x i32> %step, <n x 4 x i32> undef, <n x 4 x i32> zeroinitializer
&...