search for: wbinvd

From e2d47e2f75bac6876b7c2eaecfe946966bf27516 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Tue, 26 Nov 2013 04:53:17 +0800 Subject: [PATCH] VMX: wbinvd when vmentry under UC This patch flush cache when vmentry back to UC guest, to prevent cache polluted by hypervisor access guest memory during UC mode. However, wbinvd is a _very_ time consuming operation, so 1. wbinvd ... timer has a good possibility to expire while irq disabled, it then woul...

Since lguest was removed, only the native version of wbinvd() is used. The paravirt interface is no longer needed. Signed-off-by: Josh Poimboeuf <jpoimboe at redhat.com> --- arch/x86/include/asm/paravirt.h | 5 ----- arch/x86/include/asm/paravirt_types.h | 1 - arch/x86/include/asm/special_insns.h | 7 +------ arch/x86/kernel/paravirt.c...

...t; Date: Thu, 31 Oct 2013 06:38:15 +0800 Subject: [PATCH 4/4] XSA-60 security hole: flush cache when vmentry back to UC guest This patch flush cache when vmentry back to UC guest, to prevent cache polluted by hypervisor access guest memory during UC mode. The elegant way to do this is, simply add wbinvd just before vmentry. However, currently wbinvd before vmentry will mysteriously trigger lapic timer interrupt storm, hung booting stage for 10s ~ 60s. We still didn''t dig out the root cause of interrupt storm, so currently this patch add flag indicating hypervisor access UC guest memory to...

This patch adds "wbinvd" instruction emulation for vm86 mode. This is needed when we bring up AP of SMP VMX guest. Signed-off-by: Xin Li <xin.b.li@intel.com> diff -r 94c6fc048d8e tools/firmware/vmxassist/vm86.c --- a/tools/firmware/vmxassist/vm86.c Fri Sep 23 11:52:43 2005 +++ b/tools/firmware/vmxassist/vm...

On 04/10/17 17:58, Josh Poimboeuf wrote: > Since lguest was removed, only the native version of wbinvd() is used. > The paravirt interface is no longer needed. > > Signed-off-by: Josh Poimboeuf <jpoimboe at redhat.com> Reviewed-by: Juergen Gross <jgross at suse.com> Juergen

Fairly straightforward code motion in system.h into the sub-arch layer. Affected functionality include control register accessors, which are virtualizable but with great overhead due to the #GP cost; wbinvd, and most importantly, halt and interrupt control, which is non-virtualizable. Since read_cr4_safe can never fault on a VMI kernel (P5+ processor is required for VMI), we can omit the fault fixup, which does not play well with the VMI inline assembler, and just call read_cr4() directly. Note that...

Fairly straightforward code motion in system.h into the sub-arch layer. Affected functionality include control register accessors, which are virtualizable but with great overhead due to the #GP cost; wbinvd, and most importantly, halt and interrupt control, which is non-virtualizable. Since read_cr4_safe can never fault on a VMI kernel (P5+ processor is required for VMI), we can omit the fault fixup, which does not play well with the VMI inline assembler, and just call read_cr4() directly. Note that...

Hi. I have a very quick question. Is the instruction cache flushed by the llvm jit before code in memory is written to or executed? I'm assuming so, but I can't find where in the source code this is happening. In particular I searched for clflush, invd, and wbinvd instructions, but couldn't find them. And if it's not necessary to do this, can you please explain why? (I'm assuming the target platform has a separate L1 i-cache). Thanks. - Shasank _________________________________________________________________ Hotmail: Powerful...

...gned long native_read_cr4(void) +{ + unsigned long val; + asm volatile("movq %%cr4,%0\n\t" :"=r" (val)); + return val; +} + +static inline void native_write_cr4(unsigned long val) +{ + asm volatile("movq %0,%%cr4": :"r" (val)); +} + +static inline void native_wbinvd(void) +{ + asm volatile("wbinvd": : :"memory"); +} + +#ifdef CONFIG_PARAVIRT +#include <asm/paravirt.h> +#else /* * Clear and set 'TS' bit respectively */ -#define clts() __asm__ __volatile__ ("clts") - -static inline unsigned long read_cr0(void) -{...

...gned long native_read_cr4(void) +{ + unsigned long val; + asm volatile("movq %%cr4,%0\n\t" :"=r" (val)); + return val; +} + +static inline void native_write_cr4(unsigned long val) +{ + asm volatile("movq %0,%%cr4": :"r" (val)); +} + +static inline void native_wbinvd(void) +{ + asm volatile("wbinvd": : :"memory"); +} + +#ifdef CONFIG_PARAVIRT +#include <asm/paravirt.h> +#else /* * Clear and set 'TS' bit respectively */ -#define clts() __asm__ __volatile__ ("clts") - -static inline unsigned long read_cr0(void) -{...

..._AMD && + cx->entry_method == ACPI_CSTATE_EM_SYSIO ) + { + /* Intel prefers not to use SYSIO */ + + /* Avoid references to shared data after the cache flush */ + u32 address = cx->address; + u32 pmtmr_ioport_local = pmtmr_ioport; + + wbinvd(); + + while ( 1 ) + { + inb(address); + inl(pmtmr_ioport_local); + } } default_halt:

...t; wrote: > Hi.  I have a very quick question.  Is the instruction cache flushed by the > llvm jit before code in memory is written to or executed?  I'm assuming so, > but I can't find where in the source code this is happening.  In particular > I searched for clflush, invd, and wbinvd instructions, but couldn't find > them.  And if it's not necessary to do this, can you please explain why? > (I'm assuming the target platform has a separate L1 i-cache).  Thanks. On x86 in particular, explicitly flushing the instruction cache isn't necessary; the processor t...

...gt; .mmu_read_cr2 = { 0x0f, 0x20, 0xd0 }, // mov %cr2, %[re]ax > .mmu_read_cr3 = { 0x0f, 0x20, 0xd8 }, // mov %cr3, %[re]ax > -# ifdef CONFIG_X86_64 > .mmu_write_cr3 = { 0x0f, 0x22, 0xdf }, // mov %rdi, %cr3 > .irq_restore_fl = { 0x57, 0x9d }, // push %rdi; popfq > .cpu_wbinvd = { 0x0f, 0x09 }, // wbinvd > @@ -50,19 +45,11 @@ static const struct patch_xxl patch_data_xxl = { > 0x48, 0x0f, 0x07 }, // swapgs; sysretq > .cpu_swapgs = { 0x0f, 0x01, 0xf8 }, // swapgs > .mov64 = { 0x48, 0x89, 0xf8 }, // mov %rdi, %rax > -# else > - .mmu_write_...

...gt; .mmu_read_cr2 = { 0x0f, 0x20, 0xd0 }, // mov %cr2, %[re]ax > .mmu_read_cr3 = { 0x0f, 0x20, 0xd8 }, // mov %cr3, %[re]ax > -# ifdef CONFIG_X86_64 > .mmu_write_cr3 = { 0x0f, 0x22, 0xdf }, // mov %rdi, %cr3 > .irq_restore_fl = { 0x57, 0x9d }, // push %rdi; popfq > .cpu_wbinvd = { 0x0f, 0x09 }, // wbinvd > @@ -50,19 +45,11 @@ static const struct patch_xxl patch_data_xxl = { > 0x48, 0x0f, 0x07 }, // swapgs; sysretq > .cpu_swapgs = { 0x0f, 0x01, 0xf8 }, // swapgs > .mov64 = { 0x48, 0x89, 0xf8 }, // mov %rdi, %rax > -# else > - .mmu_write_...

...\n\t" #define write_cr4(x) \ __asm__ __volatile__("movl %0,%%cr4": :"r" (x)) -/* - * Clear and set 'TS' bit respectively - */ -#define clts() __asm__ __volatile__ ("clts") -#define stts() write_cr0(8 | read_cr0()) - -#endif /* __KERNEL__ */ - #define wbinvd() \ __asm__ __volatile__ ("wbinvd": : :"memory") + +/* Clear the 'TS' bit */ +#define clts() __asm__ __volatile__ ("clts") +#endif/* CONFIG_PARAVIRT */ + +/* Set the 'TS' bit */ +#define stts() write_cr0(8 | read_cr0()) + +#endif /* __KERNEL__ */ s...

...\n\t" #define write_cr4(x) \ __asm__ __volatile__("movl %0,%%cr4": :"r" (x)) -/* - * Clear and set 'TS' bit respectively - */ -#define clts() __asm__ __volatile__ ("clts") -#define stts() write_cr0(8 | read_cr0()) - -#endif /* __KERNEL__ */ - #define wbinvd() \ __asm__ __volatile__ ("wbinvd": : :"memory") + +/* Clear the 'TS' bit */ +#define clts() __asm__ __volatile__ ("clts") +#endif/* CONFIG_PARAVIRT */ + +/* Set the 'TS' bit */ +#define stts() write_cr0(8 | read_cr0()) + +#endif /* __KERNEL__ */ s...

...- .read_cr4 = native_read_cr4, - .read_cr4_safe = native_read_cr4_safe, - .write_cr4 = native_write_cr4, - .save_fl = native_save_fl, - .restore_fl = native_restore_fl, - .irq_disable = native_irq_disable, - .irq_enable = native_irq_enable, - .safe_halt = native_safe_halt, - .halt = native_halt, - .wbinvd = native_wbinvd, - .read_msr = native_read_msr_safe, - .write_msr = native_write_msr_safe, - .read_tsc = native_read_tsc, - .read_pmc = native_read_pmc, - .sched_clock = native_sched_clock, - .get_cpu_khz = native_calculate_cpu_khz, - .load_tr_desc = native_load_tr_desc, - .set_ldt = native_set_ldt...

...- .read_cr4 = native_read_cr4, - .read_cr4_safe = native_read_cr4_safe, - .write_cr4 = native_write_cr4, - .save_fl = native_save_fl, - .restore_fl = native_restore_fl, - .irq_disable = native_irq_disable, - .irq_enable = native_irq_enable, - .safe_halt = native_safe_halt, - .halt = native_halt, - .wbinvd = native_wbinvd, - .read_msr = native_read_msr_safe, - .write_msr = native_write_msr_safe, - .read_tsc = native_read_tsc, - .read_pmc = native_read_pmc, - .sched_clock = native_sched_clock, - .get_cpu_khz = native_calculate_cpu_khz, - .load_tr_desc = native_load_tr_desc, - .set_ldt = native_set_ldt...

...return cr8; -} - -static inline void native_write_cr8(unsigned long val) -{ - asm volatile("movq %0,%%cr8" :: "r" (val) : "memory"); -} -#endif - #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS static inline u32 rdpkru(void) { @@ -200,16 +186,6 @@ static inline void wbinvd(void) #ifdef CONFIG_X86_64 -static inline unsigned long read_cr8(void) -{ - return native_read_cr8(); -} - -static inline void write_cr8(unsigned long x) -{ - native_write_cr8(x); -} - static inline void load_gs_index(unsigned selector) { native_load_gs_index(selector); diff --git a/arch/x...

...return cr8; -} - -static inline void native_write_cr8(unsigned long val) -{ - asm volatile("movq %0,%%cr8" :: "r" (val) : "memory"); -} -#endif - #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS static inline u32 rdpkru(void) { @@ -200,16 +186,6 @@ static inline void wbinvd(void) #ifdef CONFIG_X86_64 -static inline unsigned long read_cr8(void) -{ - return native_read_cr8(); -} - -static inline void write_cr8(unsigned long x) -{ - native_write_cr8(x); -} - static inline void load_gs_index(unsigned selector) { native_load_gs_index(selector); diff --git a/arch/x...