Displaying 5 results from an estimated 5 matches for "vvmcs".
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2013 Jan 21
6
[PATCH v3 0/4] nested vmx: enable VMCS shadowing feature
...se
readonly ones. Intel SDM introduces this functionality at bit 29 in
IA32_VMX_MISC MSR.
For details, please refer to:
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
Thanks,
Dongxiao
Dongxiao Xu (4):
nested vmx: Use a list to store the launched vvmcs for L1 VMM
nested vmx: use VMREAD/VMWRITE to construct vVMCS if enabled VMCS
shadowing
nested vmx: optimize for bulk access of virtual VMCS
nested vmx: enable VMCS shadowing feature
xen/arch/x86/hvm/vmx/vmcs.c | 97 +++++++++++++++-
xen/arch/x86/hvm/vmx/vvmx.c | 234 +++...
2013 Jan 07
9
[PATCH v2 0/3] nested vmx bug fixes
Changes from v1 to v2:
- Use a macro to replace the hardcode in patch 1/3.
This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area
synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH,
and CR0/CR4 emulation.
Please help to review and pull.
Thanks,
Dongxiao
Dongxiao Xu (3):
nested vmx: emulate IA32_VMX_MISC MSR
nested vmx: synchronize page
2012 Dec 10
26
[PATCH 00/11] Add virtual EPT support Xen.
From: Zhang Xiantao <xiantao.zhang@intel.com>
With virtual EPT support, L1 hyerpvisor can use EPT hardware
for L2 guest''s memory virtualization. In this way, L2 guest''s
performance can be improved sharply. According to our testing,
some benchmarks can show > 5x performance gain.
Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com>
Zhang Xiantao (11):
2013 Sep 23
57
[PATCH RFC v13 00/20] Introduce PVH domU support
This patch series is a reworking of a series developed by Mukesh
Rathor at Oracle. The entirety of the design and development was done
by him; I have only reworked, reorganized, and simplified things in a
way that I think makes more sense. The vast majority of the credit
for this effort therefore goes to him. This version is labelled v13
because it is based on his most recent series, v11.
2012 Oct 02
18
[PATCH 0/3] x86: adjust entry frame generation
This set of patches converts the way frames gets created from
using PUSHes/POPs to using MOVes, thus allowing (in certain
cases) to avoid saving/restoring part of the register set.
While the place where the (small) win from this comes from varies
between CPUs, the net effect is a 1 to 2% reduction on a
combined interruption entry and exit when the full state save
can be avoided.
1: use MOV