search for: vmcs

...te the VMREAD/VMWRITE bitmap instead of xenheap. Changes from v1 to v2: - Use domain_page_map_to_mfn() instead of virt_to_mfn() to get the machine frame. - Address other comments from Jan, including some programming format, return value type, etc. Latest Intel SDM introduced a new feature "VMCS shadowing" at bit 14 in Secondary Processor-Based VM-Execution Controls for nested virtualization. The main purpose of this feature is to reduce or eliminate the number of VM exit for non-root VMREAD and VMWRITE. It provides the capability to link a "virtual VMCS" with the current r...

The attached patch uses per-cpu vmcs pointer to avoid unnecessary vmcs loading in vmx_do_resume(); Signed-off-by: Eric Liu <eric.e.liu@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

vmwrite higher 32 bits of 64bit VMCS fields when in PAE mode. Signed-off-by: Xin Li <xin.b.li@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

From 291adaf4ad6174c5641a7239c1801373e92e9975 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Thu, 28 Nov 2013 05:26:06 +0800 Subject: [PATCH v4 3/7] X86: MPX IA32_BNDCFGS msr handle When MPX supported, a new guest-state field for IA32_BNDCFGS is added to the VMCS. In addition, two new controls are added: - a VM-exit control called "clear BNDCFGS" - a VM-entry control called "load BNDCFGS." VM exits always save IA32_BNDCFGS into BNDCFGS field of VMCS. Signed-off-by: Xudong Hao <xudong.hao@intel.com> Reviewed-by: Liu Jinsong <j...

Split VMCS initialization function into guest/host/control 3 parts. Signed-off-by: Xin Li <xin.b.li@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

...x86/hvm/svm/vmcb.c @@ -310,7 +310,7 @@ static struct keyhandler vmcb_dump_keyha .desc = "dump AMD-V VMCBs" }; -void setup_vmcb_dump(void) +void __init setup_vmcb_dump(void) { register_keyhandler(''v'', &vmcb_dump_keyhandler); } --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -1492,7 +1492,7 @@ static struct keyhandler vmcs_dump_keyha .desc = "dump Intel''s VMCS" }; -void setup_vmcs_dump(void) +void __init setup_vmcs_dump(void) { register_keyhandler(''v'', &vmcs_dump_keyhandler);...

...main_resources() will not reduce the refcnt of the domain to 0, therefore the latter vcpu release functions will not be called. To fix this issue, we need to release the nv_vvmcx and io_bitmaps in relinquish_domain_resources(). Besides, after destroy the nested vcpu, we need to switch the vmx->vmcs back to the L1 and let the vcpu_destroy() logic to free the L1 VMCS page. Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com> --- xen/arch/x86/hvm/hvm.c | 3 +++ xen/arch/x86/hvm/vmx/vmx.c | 3 ++- xen/arch/x86/hvm/vmx/vvmx.c | 11 +++++++++++ xen/include/a...

Changes from v1 to v2: - Use a macro to replace the hardcode in patch 1/3. This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH, and CR0/CR4 emulation. Please help to review and pull. Thanks, Dongxiao Dongxiao Xu (3): nested vmx: emulate IA32_VMX_MISC MSR nested vmx: synchronize page fault error code match and mask nested vmx: f...

This patch removes the ignored "Unconditional I/O exiting" setting in VMCS for the vmx guest since "Use I/O bitmaps" setting is being used. -Himanshu -- ------------------------------------------------------------------------- Himanshu Raj PhD Student, GaTech (www.cc.gatech.edu/~rhim) I prefer to receive attachments in an open, non-proprietary format. --------...

Attached is patch for HVM guests (VMX only) that prints VMCS areas for all vcpus. A new hotkey (''v'') triggers the dump. We also print VMCS for current processor when vmenter fails. -boris _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

...no effect on the behavior of RDMSR/WRMSR if the "virtualize x2APIC mode" VM-execution control is 0. When guest uses x2APIC mode, we should enable "virtualize x2APIC mode" for APICV first. Signed-off-by: Jiongxi Li <jiongxi.li@intel.com> diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index de22e03..4807eb2 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -190,7 +190,8 @@ static int vmx_init_vmcs_config(void) */ if ( _vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW ) opt |= SECONDA...

This patch removes the ignored "Unconditional I/O exiting" setting in VMCS for the vmx guest since "Use I/O bitmaps" setting is being used. Signed-off by Himanshu Raj (rhim@cc.gatech.edu) diff -r 19c55935580f xen/include/asm-x86/hvm/vmx/vmx.h --- a/xen/include/asm-x86/hvm/vmx/vmx.h Wed Apr 12 17:53:38 2006 +++ b/xen/include/asm-x86/hvm/vmx/vmx.h Thu Apr 13 02:...

Hi all, I have some puzzle about hvmloader in the path /tools/firmware/, they are: 1: Is hvmloader running in non-root mode? 2: If hvmloader runs in non-root mode, does it have its pagetable? when set GUEST_CR3 in vmcs? 3: How can I find the value of GUEST_RIP in vmcs is set to the entry point of hvmloader,when virtual machine do it first vm entry. Much Thanks! - henanwxr _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

I recently realized that the original way of dealing with the DebugCtl MSR on VMX failed to make use of the dedicated guest VMCS field. This is being fixed with this patch. What is puzzling me to a certain degree is that while there is a guest VMCS field for this MSR, there''s no equivalent host load field, but there''s also no indication that the MSR would be cleared during a vmexit. Can someone at Intel pe...

...tests indicate that most spinlocks are held for less than 2^12 cycles. Performance tests show that with 2X LP over-commitment we can get +2% perf improvement for kernel build(Even more perf gain with more LPs). Signed-off-by: Zhai Edwin <edwin.zhai@intel.com> Index: hv/xen/arch/x86/hvm/vmx/vmcs.c =================================================================== --- hv.orig/xen/arch/x86/hvm/vmx/vmcs.c +++ hv/xen/arch/x86/hvm/vmx/vmcs.c @@ -44,6 +44,20 @@ boolean_param("vpid", opt_vpid_enabled); static int opt_unrestricted_guest_enabled = 1; boolean_param("unrestricted_gu...

...et vcpu is not running or there already a notification event pending in the vcpu, do nothing. The interrupt will be handled by next vm entry Refer to Intel SDM vol3, 29.6 to get more information. Yang Zhang (4): VMX: Detect posted interrupt capability VMX: Turn on posted interrupt bit in vmcs VMX: Add posted interrupt supporting VMX: Use posted interrupt to deliver virutal interrupt xen/arch/x86/hvm/vioapic.c | 4 +- xen/arch/x86/hvm/vlapic.c | 19 +++++- xen/arch/x86/hvm/vmsi.c | 5 +- xen/arch/x86/hvm/vmx/vm...

...> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> CC: Keir Fraser <keir@xen.org> CC: Jan Beulich <JBeulich@suse.com> CC: Tim Deegan <tim@xen.org> CC: Jun Nakajima <jun.nakajima@intel.com> CC: Eddie Dong <eddie.dong@intel.com> --- xen/arch/x86/hvm/vmx/vmcs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 290b42f..4aab971 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -950,6 +950,7 @@ static int construct_vmcs(struct vcpu *v) vmx_disable_i...

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

...tual_intr_delivery_enabled(void) return cpu_has_vmx_virtual_intr_delivery; } +static void vmx_process_isr(int isr, struct vcpu *v) +{ + unsigned long status; + u8 old; + + if ( !cpu_has_vmx_virtual_intr_delivery ) + return; + + if (isr < 0) + isr = 0; + + vmx_vmcs_enter(v); + status = __vmread(GUEST_INTR_STATUS); + old = status >> VMX_GUEST_INTR_STATUS_SVI_OFFSET; + if (isr != old) { + status &= VMX_GUEST_INTR_STATUS_SUBFIELD_BITMASK; + status |= isr << VMX_GUEST_INTR_STATUS_SVI_OFFSET; + __vmwrite(GUEST_INTR_STA...

...6_FEATURE_SMEP); + + /* Not expose INVPCID to non-hap hvm */ + if ( (count == 0) && !hap_enabled(d) ) + *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); break; case 0xb: /* Fix the x2APIC identifier. */ diff -r c61a5ba8c972 xen/arch/x86/hvm/vmx/vmcs.c --- a/xen/arch/x86/hvm/vmx/vmcs.c Tue Nov 22 02:47:51 2011 +0800 +++ b/xen/arch/x86/hvm/vmx/vmcs.c Tue Nov 22 16:15:19 2011 +0800 @@ -183,7 +183,8 @@ static int vmx_init_vmcs_config(void) SECONDARY_EXEC_WBINVD_EXITING | SECONDARY_EXEC_ENABLE_EPT | S...