search for: vts

...rt my weekly to monthly data in order to have the same periodicity in all of them. I've read that package xts can help me with this issue, so I have done the following script: *ini_week<-as.Date("2010-09-19") final_week<-seq(ini_week, length.out=104, by = "1 week") vts<-read.csv("C:/DATA.csv",header = TRUE) vts<-vts[,2] wvts<-xts(vts, order.by=final_week) mes<-apply.monthly(wvts,sum) *A portion of the result is this one: [,1] 2010-09-26 2.9 2010-10-31 8.5 2010-11-28 5.8 2010-12-26 5.5 2011-01-30 7.5 .... It seem to be qui...

...than pid$target::FunName:entry and return? I heard somewhere that $target does not need to be used with static probes but the probes don''t show up unless Firefox is running and then only as mozillaNNNNN, i.e. mozilla$target. Thanks, Joel --- BEGIN { self->ts = 0; self->vts = 0; } mozilla$target:::process-xul-reflow-entry { self->ts = timestamp; self->vts = vtimestamp; self->roots = arg0; } mozilla$target:::process-xul-reflow-return /self->ts/ { this->ts = timestamp - self->ts; this->vts = vtimestamp - self->vts; printf(&qu...

...return "PPCISD::TAILCALL"; + case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; } } @@ -2726,33 +2727,13 @@ SDOperand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Lab...

....d and 17.9s when tracing with it. Now the question... Should I be looking at the elapsed time above in the context of 0.9s or 17.9s? Thanks, Joel --- [1] sigcont.d BEGIN { system("kill -CONT %d &\n", $target); } [2] menu-construct.d BEGIN { self->ts = 0; self->vts = 0; } pid$target::nsMenuX??MenuConstruct*:entry { self->ts = timestamp; self->vts = vtimestamp; } pid$target::nsMenuX??MenuConstruct*:return /self->ts/ { this->ts = timestamp - self->ts; this->vts = vtimestamp - self->vts; @tsint = sum(this->ts / 1000000); @ts...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...return "PPCISD::TAILCALL"; + case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; } } @@ -2726,33 +2727,13 @@ SDOperand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Lab...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...return "PPCISD::TAILCALL"; + case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; } } @@ -2726,33 +2727,13 @@ SDOperand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Lab...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

(2nd attempt, the mailing list is still bouncing some gmail SMTP servers because of the multihop DSBL.) Over the weekend I installed CentOS 5 on my hp pavilion ze5300. The graphical install went just fine, and everything (except wireless, haven't worked on that yet) seems to be working. However, on boot, the text console comes up. If I hit Alt-F7 manually, I'm switched to the

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...return "PPCISD::TAILCALL"; + case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; } } @@ -2726,33 +2727,13 @@ SDOperand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Lab...

Does dtrace have a problem catching the return from memset on Mac OSX? The script below catches the entry just fine but the return clause is never entered. Thanks, Joel --- pid$target::memset:entry /arg1 == 0/ { self->size = arg2; self->ts = timestamp; self->vts = vtimestamp; } pid$target::memset:return /self->size/ { @ts = sum(timestamp - self->ts); @vts = sum(vtimestamp - self->vts); @size = sum(self->size); @count = count(); self->ts = 0; self->vts = 0; self->size = 0; } END { printa("elapsed: %@u\n&q...

...e MVT::ValueType of a MachineInstruction > MachineOperand? For example, the register operand of an x86 MOVAPD > should > have an MVT::ValueType of v2f64. A MOVAPS register operand should > have an > MVT::ValueType of v4f32. The short answer is no. A op of a number of different VTs can map to the same instruction. However, given a register class you can get to the list of VTs that map to it. Take a look at TargetRegisterDesc. Evan > > > So given a MachineInstruction and its MachineOperands is there some > easy way > to derive this information? I don...

...st time I asked about it I was > told that fixing it would be too hard/expensive. I know, and it's somewhat unfortunate. However, this path is extremely hot in LLC, and was significantly contended using only two threads. I don't have a non-contended solution offhand. >> VTs[VT.getSimpleVT().SimpleTy] = VT; >> - return &VTs[VT.getSimpleVT().SimpleTy]; >> + sys::MemoryFence(); > > I don't think this fence actually does anything useful unless > users of the pointer do a fence before reading the contents > of the pointer. That said,...

Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return

Is there an easy way to get the MVT::ValueType of a MachineInstruction MachineOperand? For example, the register operand of an x86 MOVAPD should have an MVT::ValueType of v2f64. A MOVAPS register operand should have an MVT::ValueType of v4f32. So given a MachineInstruction and its MachineOperands is there some easy way to derive this information? I don't see anything in TargetInstrInfo