Displaying 2 results from an estimated 2 matches for "vsqrtssm".
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vsqrtss
2014 Sep 18
3
[LLVMdev] predicates vs. requirements [TableGen, X86InstrInfo.td]
...scalar unary operations, fold a load into the operation
// only in OptForSize mode. It eliminates an instruction, but it also
// eliminates a whole-register clobber (the load), so it introduces a
// partial register update condition.
def : Pat<(f32 (fsqrt (load addr:$src))),
(VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
Requires<[HasAVX, OptForSize]>;
This is generated:
vsqrtss (%rdi), %xmm0, %xmm0
regardless of whether I specify -Os or -O1 with clang.
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2014 Sep 19
2
[LLVMdev] predicates vs. requirements [TableGen, X86InstrInfo.td]
...ation
> > // only in OptForSize mode. It eliminates an instruction, but it also
> > // eliminates a whole-register clobber (the load), so it introduces a
> > // partial register update condition.
> > def : Pat<(f32 (fsqrt (load addr:$src))),
> > (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
> > Requires<[HasAVX, OptForSize]>;
> >
> > This is generated:
> > vsqrtss (%rdi), %xmm0, %xmm0
> >
> > regardless of whether I specify -Os or -O1 with clang.
>
> You might want to take a look...