search for: vsqrtss

...scalar unary operations, fold a load into the operation // only in OptForSize mode. It eliminates an instruction, but it also // eliminates a whole-register clobber (the load), so it introduces a // partial register update condition. def : Pat<(f32 (fsqrt (load addr:$src))), (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX, OptForSize]>; This is generated: vsqrtss (%rdi), %xmm0, %xmm0 regardless of whether I specify -Os or -O1 with clang. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.l...

...ation > > // only in OptForSize mode. It eliminates an instruction, but it also > > // eliminates a whole-register clobber (the load), so it introduces a > > // partial register update condition. > > def : Pat<(f32 (fsqrt (load addr:$src))), > > (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>, > > Requires<[HasAVX, OptForSize]>; > > > > This is generated: > > vsqrtss (%rdi), %xmm0, %xmm0 > > > > regardless of whether I specify -Os or -O1 with clang. > > You might want to take a look...

Well, you’ll probably need to specify which CPU for the instructions to be recognized as valid encodings. -mcpu=knl doesn’t seem sufficient, though, so there’s probably something more going on. Elena, do you know what’s happening here? It’s important that the disassembler work with the new instructions as well as the assembler. I looked but didn’t see any disassembler tests for avx512. -Jim On

...actually means? It seems to me the root problem here is that the instruction has two outputs and we don't want the output to be allocated to the same register as the inputs. We have no way to express multiple outputs in TableGen. As it happens, AVX has similar problems with its semantics for VSQRTSS/SD. In fact the semantics there are even worse, to the point where I'm not going to think any more about it. :) -Dave

Hi, It seems LLVM-MC is broken with Avx512? $ echo "vinserti32x4 \$1, %xmm21, %zmm5, %zmm17"|./Release+Asserts/bin/llvm-mc -assemble -arch=x86-64 -show-encoding -x86-asm-syntax=att .text vinserti32x4 $1, %xmm21, %zmm5, %zmm17 # encoding: [0x62,0xa3,0x55,0x48,0x38,0xcd,0x01] $ echo "0x62,0xa3,0x55,0x48,0x38,0xcd,0x01" |./Release+Asserts/bin/llvm-mc -disassemble

On Dec 15, 2009, at 5:08 PM, David Greene wrote: > On Tuesday 15 December 2009 18:01, Jim Grosbach wrote: > >> For a usage example, I've included in the patch the modification to >> use the constraint for the STREX ARM instruction. > > Your example is: > > constraints = "@early $success" > > Why not spell it as: > > constraints =