search for: vsetvli

On 2/5/19 1:27 AM, Philip Reames via llvm-dev wrote: > > On 1/31/19 4:57 PM, Bruce Hoult wrote: >> On Thu, Jan 31, 2019 at 4:05 PM Philip Reames via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >>> Do such architectures frequently have arithmetic operations on the >>> mask registers?  (i.e. can I reasonable compute a conservative >>> length

...The canonical example is > strlen()/strcpy(). For most code you can ignore it and say the AVL > changes only when you execute VSETVL[I]. > > - any time the program uses VSETVL[I] *both* the MVL and the AVL can change. > > - the common case is a loop with the vtype in an immediate VSETVLI at > the head of the loop. In this case, the AVL potentially changes in > every iteration of the loop (but usually only in the last one or two > iterations). As the vtype is in an immediate it can't change from > iteration to iteration. But it's common for two loops in the same...

Hi Everyone, I am wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as: %vl = call i32 @llvm.riscv.vsetvl(i32 %n) At the time of the talk (April 2019) LLVM support for the V

...uently, it would be much, much better to be able to have a > > single bit of a predicate apply to the *entire* vec3 or vec4 type, on > > each outer loop. > > This situation can be handled easily in the standard RISC-V vector > extension. You'd do something like... > > vsetvli t0, a0, vsew128,vnreg8,vdiv4 > > ... to configure the vector unit to provide eight vector register > variables divided into a standard element width of 128 bits (some > instructions will widen or narrow one step to/from 64 bits or 256 > bits), and then dividing each 128 bit element i...

--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 On Thu, Jan 31, 2019 at 10:22 PM Jacob Lifshay <programmerjake at gmail.com> wrote: > > We're in-progress designing a RISC-V extension (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) that would have variable-length vectors of short vectors (1 to 4): > <VL x <4 x

...er supports two strategies to > generate LLVM IR using scalable vectors: > > 1) Generate a vector loop using VF (vscale x k) = whole vector register > width, followed by a scalar tail loop. > > 2) Generate only a vector loop with active vector length controlled by > the RISC-V `vsetvli` instruction and using Vector Predicated intrinsics > (https://reviews.llvm.org/D57504). (Of course, intrinsics come with > their own limitations but we feel it serves as a good proof of concept > for our use case.) We also extend the VPlan to generate VPInstructions > that are expanded...

...ctor extension. The auto-vectorizer supports two strategies to generate LLVM IR using scalable vectors: 1) Generate a vector loop using VF (vscale x k) = whole vector register width, followed by a scalar tail loop. 2) Generate only a vector loop with active vector length controlled by the RISC-V `vsetvli` instruction and using Vector Predicated intrinsics (https://reviews.llvm.org/D57504). (Of course, intrinsics come with their own limitations but we feel it serves as a good proof of concept for our use case.) We also extend the VPlan to generate VPInstructions that are expanded using predicated in...

...ctor extension. The auto-vectorizer supports two strategies to generate LLVM IR using scalable vectors: 1) Generate a vector loop using VF (vscale x k) = whole vector register width, followed by a scalar tail loop. 2) Generate only a vector loop with active vector length controlled by the RISC-V `vsetvli` instruction and using Vector Predicated intrinsics (https://reviews.llvm.org/D57504). (Of course, intrinsics come with their own limitations but we feel it serves as a good proof of concept for our use case.) We also extend the VPlan to generate VPInstructions that are expanded using predicated in...