Displaying 9 results from an estimated 9 matches for "vsetvl".
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2020 Sep 29
2
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
...m wondering how to use RISC-V V (Vector) extension instructions in
LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the
Vector extension and on slide 16 [2] they show LLVM IR samples which use
the vector instructions through intrinsic functions, such as:
%vl = call i32 @llvm.riscv.vsetvl(i32 %n)
At the time of the talk (April 2019) LLVM support for the V extension
was developed out-of-tree at https://github.com/hanna-kruppe/rvv-llvm .
However, that repository is archived now and the README file indicates
that it is outdated since support for the RISC-V V extension is now
devel...
2019 Feb 05
4
[RFC] Vector Predication
On 2/5/19 1:27 AM, Philip Reames via llvm-dev wrote:
>
> On 1/31/19 4:57 PM, Bruce Hoult wrote:
>> On Thu, Jan 31, 2019 at 4:05 PM Philip Reames via llvm-dev
>> <llvm-dev at lists.llvm.org> wrote:
>>> Do such architectures frequently have arithmetic operations on the
>>> mask registers? (i.e. can I reasonable compute a conservative
>>> length
2020 Oct 29
0
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
...vm.org/pipermail/llvm-dev/2020-October/145850.html <http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html> which includes links to proposed upstream patches implementing the RFC's approach.
I'm not sure the status of that RFC with respect to intrinsics for operations like vsetvl - but it seems likely to me that such an operation will be managed at a lower level than LLVM intrinsics. I hope someone like Roger or Evandro can chime in with their intentions with respect to this behaviour.
Sam
> On 29 Sep 2020, at 12:30 pm, Michael Platzer via llvm-dev <llvm-dev at lis...
2016 Nov 28
2
[RFC] Supporting ARM's SVE in LLVM
...>
> and I'm looking forward to his update at the RISC-V Workshop this
> Wednesday, not least because I'm hoping he'll have done my homework
> for me and contrast his proposal to what is publicly known about SVE.
Thanks! This is really helpful!
> The proposal includes a vsetvl instruction (slide 20) which returns
> the minimum of the hardware vector length and requested vector length.
I haven't seen a similar instruction in SVE yet, but the compulsory
predicate on all instructions kinda make that redundant, since you can
always use it to calculate the number of &...
2019 Feb 05
3
[RFC] Vector Predication
...st
> six or twelve months as it's gotten closer to being set in stone.
>
> The way it has ended up (very unlikely to change now) is:
>
> - any given RVV vector unit has 32 registers each with the same and
> fixed length in bits.
>
> - the vector unit is configured by the VSETVL[I] instruction which has
> two arguments: 1) the requested AVL, and 2) the vtype (vector type).
>
> - The vtype is an integer with several small fields, of which two are
> currently defined (the other bits must be zero). The fields are the
> Standard Element Width and VLMul. SEW can...
2016 Nov 27
2
[RFC] Supporting ARM's SVE in LLVM
On 27 November 2016 at 16:51, Amara Emerson <amara.emerson at gmail.com> wrote:
> There is nothing to stop other targets from using
> stepvector/seriesvector. In fact for wide vector targets, often the IR
> constant for representing a step vector is explicitly expressed as
> <i32 0, i32 1, i32 2..> and so on (this gets really cumbersome when
> your vector length is
2019 Mar 19
3
Scalable Vector Types in IR - Next Steps?
On Tue, Mar 19, 2019 at 4:11 AM Graham Hunter <Graham.Hunter at arm.com> wrote:
> Hi Eric and Chandler,
>
> I appreciate your concerns; I don't think the impact will be that great,
> but then it's
> rather easy for me to keep SVE in mind when working on other parts of the
> codebase
> given how long I've spent working on it.
>
> Are there any
2019 Oct 02
2
Adding support for vscale
...mechanism for obtaining VLMAX, which is directly related to VLEN (so you
can obtain VLEN with a little more arithmetic, though for most purposes
VLMAX is more useful): requesting the vector length of -1 (unsigned: 2^XLEN
- 1) is guaranteed to result in vl=VLMAX.
For regular strip-mined loops, the vsetvl instruction takes care of
everything so there's simply no need for the program to do this. But for
other tasks, it's required (i.e., you can't sensibly write the program
otherwise) and perfectly fine w.r.t. portability. One example is the stack
frame layout when there's any vectors...
2019 Oct 01
2
Adding support for vscale
Hi Luke,
> was it intentional to leave out both jacob and myself?
> [...]
> if that was a misunderstanding or an oversight i apologise for raising it.
It was definitely not my intention to be non-inclusive, my apologies if that seemed the case!
> can i therefore recommend a change, here:
> [...]
> "This patch adds vscale as a symbolic constant to the IR, similar to
>