search for: vrpim_2048

You are right. But when i defined my instruction as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; I get opcode conflicts? Then what to do? On Tue, Sep 5, 2017 at 3:51 AM, Craig Topper <craig.topper at gmail.com> wrote: >...

...oth. > > ~Craig > > On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> You are right. But when i defined my instruction as follows: >> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins >> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; >> >> I get opcode conflicts? Then what to do? >> >> On Tue, Sep 5, 2017 at 3:51 AM, Craig To...

...Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com> >>> wrote: >>> >>>> You are right. But when i defined my instruction as follows: >>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins >>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; >>>> >>>> I get opcode conflicts? Then what to do? >>>> >>&...

...t;hahmed2305 at gmail.com> >>>>> wrote: >>>>> >>>>>> You are right. But when i defined my instruction as follows: >>>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins >>>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >>>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; >>>>>> >>>>>> I get opcode conflicts? Then what t...

Thank You. My add instruction has TA as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; so i defined; bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; n...

...t;>>>> wrote: >>>>>>> >>>>>>>> You are right. But when i defined my instruction as follows: >>>>>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins >>>>>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >>>>>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; >>>>>>>> >>>>>>>> I g...

Hello, I am trying to emit binary for my implemented vector instructions. Although yet i havent done any change or addition in MC framework, For vector load instruction there are no error coming. But for vector add instruction is something like this; > %R_0_REG2048b_1<def> = P_256B_VADD %R_0_REG2048b_1<kill>, %R_0_REG2048b_0<kill> I am getting the following error: Unknown

...Please help me. On Mon, Aug 7, 2017 at 12:03 AM, hameeza ahmed <hahmed2305 at gmail.com> wrote: > I am trying to implement vector shuffle for v64i32. Is the following > correct? > > > def VSHUFFLE_256B : I<0xE8, MRMDestReg, (outs VR_2048:$dst), > (ins VR_2048:$src1, VRPIM_2048:$src2),"VSHUFFLE_256B\t{$src1, $src2, > $dst|$dst, $src1, $src2}", > [(set VR_2048:$dst, (shufflevector (v64i32 VR_2048:$src1), (v64i32 > VR_2048:$src2)))]>, TA; > > Please help. > > > > > On Sun, Aug 6, 2017 at 11:48 PM, hameeza ahmed <hahmed2305 at gm...

...d <hahmed2305 at gmail.com> >> wrote: >> >>> I am trying to implement vector shuffle for v64i32. Is the following >>> correct? >>> >>> >>> def VSHUFFLE_256B : I<0xE8, MRMDestReg, (outs VR_2048:$dst), >>> (ins VR_2048:$src1, VRPIM_2048:$src2),"VSHUFFLE_256B\t{$src1, $src2, >>> $dst|$dst, $src1, $src2}", >>> [(set VR_2048:$dst, (shufflevector (v64i32 VR_2048:$src1), (v64i32 >>> VR_2048:$src2)))]>, TA; >>> >>> Please help. >>> >>> >>> >>>...

...ing to implement vector shuffle for v64i32. Is the following >>>>>>> correct? >>>>>>> >>>>>>> >>>>>>> def VSHUFFLE_256B : I<0xE8, MRMDestReg, (outs VR_2048:$dst), >>>>>>> (ins VR_2048:$src1, VRPIM_2048:$src2),"VSHUFFLE_256B\t{$src1, >>>>>>> $src2, $dst|$dst, $src1, $src2}", >>>>>>> [(set VR_2048:$dst, (shufflevector (v64i32 VR_2048:$src1), (v64i32 >>>>>>> VR_2048:$src2)))]>, TA; >>>>>>> >>>&g...